Transmitter Block Diagram - 1.0 English - PG205

SMPTE UHD-SDI LogiCORE IP Product Guide (PG205)

Document ID
PG205
Release Date
2024-06-14
Version
1.0 English

The following block diagram shows a block diagram of the SMPTE UHD-SDI transmitter. Up to sixteen SDI data streams (tx_ds1_in through tx_ds16_in) enter the transmitter and first go through the ST 352 insertion modules where ST 352 payload ID packets are optionally inserted. The data streams output from the ST 352 insertion modules are called tx_ds1_st352_out through tx_ds16_st352_out. These streams are output so that the customer application can insert ancillary data after ST 352 packets are inserted. The remaining portion of the transmitter can either use the streams output by the ST 352 packet insertion modules directly or the sixteen tx_ds1_anc_in through tx_ds16_anc_in data streams from the customer application ancillary data insertion function. Note that if the tx_dsn_anc_in data streams are used, they must be full SDI data streams, not just ancillary data.

Most frequently, ST 352 packets are only inserted into the Y data stream of each Y/C data stream pair. However, in 3G-SDI level A mode-only, ST 352 packets must be inserted into both data stream 1 and data stream 2. Muxes in the SMPTE UHD-SDI transmitter allow data stream 2 to be routed through the second ST 352 insertion module in 3G-SDI level A mode to allow that module to insert ST 352 packets into data stream 2, whereas normally data stream 3 is handled by the second ST 352 insertion module. The SMPTE UHD-SDI core has the capability to insert ST 352 packets into the C data stream and can be controlled using a parameter.

Each Y/C pair of data streams then goes through a stream processing block which optionally does line number insertion and CRC generation and insertion. Following stream processing, the data streams are interleaved by the stream MUX. This results in a multiplexed SDI data stream that is 40, 20, or 10 bit wide depending on the SDI mode. For 6G-SDI and 12G-SDI, the sync bit insertion algorithm is performed to reduce run lengths. Then the multiplexed data stream is scrambled by the SDI scrambler. In SD-SDI mode, the 10-bit scrambled data stream is processed by the SD-SDI bit replication module to replicate each bit 11 times to create a 270 Mb/s SDI serial stream with the serial transceiver TX running at 2.97 Gb/s. Finally, the data is output on the tx_txdata port to the serial transceiver to be serialized.

Figure 1. SMPTE UHD-SDI TX Block Diagram