This chapter contains information about the test bench provided in the Vivado Design Suite.
As shown in Figure 1, the demonstration test bench is a simple System Verilog module which generates all the supported SMPTE test patterns (SD-SDI, 3G-SDI, 6G-SDI, and 12G-SDI). The Test Pattern Generator (TPG) drives the SDI data to the core transmitter, which is loop backed to the core receiver. The output of the core receiver is driven to the SDI slave which performs the protocol and data check. The shaded blocks in the following figure are the System Verilog modules and the data recovery unit (DRU) block is Verilog.
Important: This simulation test bench is used to
run simulation on the UHD-SDI data core. It does not include serial transceiver
integration.
The location of the demonstration test bench is <Project_1>.gen/Sources_1/ip/<ip_name>/demo_tb.
Figure 1. SMPTE UHD-SDI Test Bench
