TX Ports - 1.0 English - PG205

SMPTE UHD-SDI LogiCORE IP Product Guide (PG205)
Document ID
PG205
Release Date
2024-06-14
Version
1.0 English

All ports are synchronous with tx_clk.

Table 1. Transceiver Ports
Port Name I/O Description
tx_clk I This clock input clocks the SDI transmitter data path. It should be driven by the same clock that drives the txusrclk port of the serial transceiver, typically the serial transceiver signal, txoutclk, after being buffered by a global clock buffer.
tx_ce I This is the clock enable input for the main portion of the transmitter data path. This is somewhat equivalent to the tx_din_rdy port of the old core. It must be High in SD, HD, and 3GA modes. In 3GB mode, it must have a 50% duty cycle. In 6G and 12G modes, it must have a 100% duty cycle when 4 streams are interleaved, 50% duty cycle when 8 streams are interleaved, and 25% duty cycle when all 16 data streams are interleaved.
tx_sd_ce I This is the clock enable for SD-SDI mode. It must have exactly a 5/6/5/6 cadence in SD-SDI mode and must be High in all other modes. This is the same as the tx_ce port of the old core.
tx_edh_ce I This is the clock enable for the TX EDH processor. In SD-SDI mode, it must be exactly equal to the tx_sd_ce port with its 5/6/5/6 cadence. It must be phase aligned with tx_sd_ce. In all other modes, this ce can be driven Low to reduce the power consumed by the EDH processor.
tx_rst I This is a synchronous reset input. It resets the transmitter when High. In order to fully reset the transmitter, the tx_ce, tx_sd_ce, and tx_edh_ce inputs must be High when tx_rst is asserted.
tx_mode[2:0] I

This input port is used to select the transmitter SDI mode:

000 = HD

001 = SD

010 = 3G

100 = 6G

101 = 12G
tx_insert_crc I When this input is High, the transmitter generates and inserts CRC values into the data streams for each video line in all modes except SD-SDI. When this input is Low, CRC values are not inserted into the data streams. This input is ignored in SD-SDI mode.
tx_insert_ln I When this input is High, the transmitter inserts line numbers into all active data streams after the EAV of each video line. The line numbers must be supplied on the tx_line_chn input ports of all active data stream pairs. When this input is Low, line numbers are not inserted. This input is ignored in SD-SDI mode.
tx_insert_st352 I When this input is High, ST 352 packets are inserted into the Y channel of the data streams, otherwise the packets are not inserted. ST 352 packets are mandatory in 3G, 6G, and 12G modes and optional in HD and SD modes. This is identical to the tx_insert_vpid port on previous core.
tx_overwrite_st352 I If this input is High, ST 352 packets already present in the data streams are overwritten. If this input is Low, existing ST 352 packets are not overwritten. This is identical to the tx_overwrite_vpid port on the previous core.
tx_insert_edh I When this input is High, the transmitter generates and inserts EDH packets into every field in SD-SDI mode. When this input is Low, EDH packets are not inserted. This input is ignored in all modes except SD-SDI mode.
tx_mux_pattern[2:0] I

This specifies the data stream interleaving pattern to be used.

000 = SD, HD, and 3G level A

001 = 3G level B

010 = 8 stream interleave in 6G and 12G modes

011 = 4 stream interleave in 6G mode

100 = 16 stream interleave in 12G mode

Note that this port replaces the function of the tx_level_b_3g port of the old core.
tx_insert_sync_bit I In 6G and 12G modes, when this port is High, the sync bit insertion function is enabled for run length mitigation. For compliance with the ST 2081 and ST 2082 standards, sync bit insertion must be enabled. However, some early implementations of 6G-SDI and 12G-SDI receivers do not support sync bit insertion and when transmitting signals to those devices, sync bit insertion can be disabled by setting this port Low.
tx_sd_bitrep_bypass I This input bypasses the 11X bit replicator used in SD-SDI mode when High. For normal operation with Xilinx serial transceiver transmitters, this input must be Low so that the bit replicator function is active.
tx_line_ch0[10:0] I Line number input for ds1 and ds2. Equivalent to tx_line_a port of old core. Note that for a single video format, all tx_line_dsX ports normally get the same line number. The only reasons to apply different line numbers to different tx_line_dsX ports are when aggregating video streams or to apply different line numbers to the data streams when transporting 1080p 50, 59.94, or 60 Hz video using 3G-SDI level B.
tx_line_ch1[10:0] I Line number input for ds3 and ds4. Equivalent to tx_line_b port of old core.
tx_line_ch2[10:0] I Line number input for ds5 and ds6.
tx_line_ch3[10:0] I Line number input for ds7 and ds8.
tx_line_ch4[10:0] I Line number input for ds9 and ds10.
tx_line_ch5[10:0] I Line number input for ds11 and ds12.
tx_line_ch6[10:0] I Line number input for ds13 and ds14.
tx_line_ch7[10:0] I Line number input for ds15 and ds16.
tx_st352_line_f1[10:0] I The ST 352 packets are inserted into the HANC space of the line number specified by this input port. For interlaced video, this input port specifies a line number in field 1. For progressive video, this specifies the only line in the frame where the packets are inserted. The input value must be valid during the entire HANC interval. If tx_insert_st352 is Low, this input is ignored. This is the same as the tx_vpid_line_f1 port of the old core.
tx_st352_line_f2[10:0] I For interlace video, ST 352 packets are inserted on the line number in field 2 indicated by this value. For progressive video, this input port must be disabled by driving the tx_st352_f2_en port Low. The input value on this port must be valid during the entire HANC interval. This port is ignored if either tx_insert_st352 or tx_st352_f2_en are Low. This is the same as the tx_vpid_line_f2 port of the old core.
tx_st352_f2_en I This input controls whether or not ST 352 packets are inserted on the line indicated by tx_vpid_line_f2. For interlaced video, this input must be High if ST 352 packet insertion is enabled. For progressive video, this input must be Low if ST 352 packet insertion is enabled. If ST 352 packet insertion is disabled (tx_insert_st352 = Low), this port is ignored. This port is identical to the tx_vpid_line_f2_en port of the old core.
tx_st352_data_ch0[31:0] I The four data bytes of the ST 352 packet to be inserted into ds1 when tx_insert_st352 is High. The data bytes are ordered like this: {byte4, byte3, byte2, byte1}. This replaces the tx_vpid_byteX ports of the old core.
tx_st352_data_ch1[31:0] I The four data bytes of the ST 352 packet to be inserted into ds3 when tx_insert_st352 is High. In 3GA mode, this port specifies the data bytes that is inserted into the ST 352 packet of ds2.
tx_st352_data_ch2[31:0] I The four data bytes of the ST 352 packet to be inserted into ds5 when tx_insert_st352 is High.
tx_st352_data_ch3[31:0] I The four data bytes of the ST 352 packet to be inserted into ds7 when tx_insert_st352 is High.
tx_st352_data_ch4[31:0] I The four data bytes of the ST 352 packet to be inserted into ds9 when tx_insert_st352 is High. Enabled only when 12G-SDI 16DS is selected.
tx_st352_data_ch5[31:0] I The four data bytes of the ST 352 packet to be inserted into ds11 when tx_insert_st352 is High. Enabled only when 12G-SDI 16DS is selected.
tx_st352_data_ch6[31:0] I The four data bytes of the ST 352 packet to be inserted into ds13 when tx_insert_st352 is High. Enabled only when 12G-SDI 16DS is selected.
tx_st352_data_ch7[31:0] I The four data bytes of the ST 352 packet to be inserted into ds15 when tx_insert_st352 is High. Enabled only when 12G-SDI 16DS is selected.
tx_insert_c_str_st352_in I When this input is High, ST 352 packets are inserted into the C channel of the data streams; otherwise the packets are not inserted. ST 352 packets are mandatory in 3G, 6G, and 12G modes and optional in HD and SD modes.
tx_st352_str_switch_3g_a_in I Setting this bit to 1'b1 uses the ST 352 payload of the tx_st352_data_ch0_c[31:0] stream instead of tx_st352_data_ch2[31:0] and the C_TX_INSERT_C_STR_ST352 parameter should be selected by the user.
tx_st352_data_ch0_c[31:0] I ST 352 data for C-stream of channel 0 and is inserted into DS2.
tx_st352_data_ch1_c[31:0] I ST 352 data for C-stream of channel 0 and is inserted into DS4
tx_st352_data_ch2_c[31:0] I ST 352 data for C-stream of channel 0 and is inserted into DS6
tx_st352_data_ch3_c[31:0] I ST 352 data for C-stream of channel 0 and is inserted into DS8
tx_st352_data_ch4_c[31:0] I ST 352 data for C-stream of channel 4 and is inserted into DS10. Enabled only when 12G-SDI 16DS is selected
tx_st352_data_ch5_c[31:0] I ST 352 data for C-stream of channel 5 and is inserted into DS12. Enabled only when 12G-SDI 16DS is selected
tx_st352_data_ch6_c[31:0] I ST 352 data for C-stream of channel 6 and is inserted into DS14. Enabled only when 12G-SDI 16DS is selected
tx_st352_data_ch7_c[31:0] I ST 352 data for C-stream of channel 7 and is inserted into DS16. Enabled only when 12G-SDI 16DS is selected
tx_ds1_in[9:0] I Data stream 1 input: SD=Y/C, HD=Y, 3GA=DS1(Y), 3GB=AY, 6G/12G=DS1. This is the same as the tx_video_a_y_in port of the old core.
tx_ds2_in[9:0] I Data stream 2 input: HD=C, 3GA=DS2(C), 3GB=AC, 6G/12G=DS2. This is the same as the tx_video_a_c_in port of the old core.
tx_ds3_in[9:0] I Data stream 3 input: 3 GB=BY, 6G/12G=DS3. This is the same as the tx_video_b_y_in port of the old core.
tx_ds4_in[9:0] I Data stream 4 input: 3GB=BC, 6G/12G=DS4. This is the same as the tx_video_b_c_in port of the old core.

tx_ds5_in though

tx_ds16_in[9:0]

 I Data stream DS5 through DS16 inputs. These are only used when doing 8 stream or 16 stream interleaving.
tx_ds1_st352_out[9:0] O This is the DS1 output for ANC data insertion. This is the same as the tx_ds1a_out port of the old core.
tx_ds2_st352_out[9:0] O This is the DS2 output for ANC data insertion. This is the same as the tx_ds2a_out port of the old core.
tx_ds3_st352_out[9:0] O This is the DS3 output for ANC data insertion. This is the same as the tx_ds1b_out port of the old core.
tx_ds4_st352_out[9:0] O This is the DS4 output for ANC data insertion. This is the same as the tx_ds2b_out port of the old core.

tx_ds5_st352_out[9:0]

through

tx_ds16_st352_out[9:0]

 O These are the DS5 through DS16 output ports after the ST 352 insertion. These data streams are made available for other ANC data insertion. The number of these ports that are active depends on the number of data streams being interleaved.
tx_ds1_anc_in[9:0] I DS1 input after ANC packet insertion. This is the same as the tx_ds1a_in port of the old core.
tx_ds2_anc_in[9:0] I DS2 input after ANC packet insertion. This is the same as the tx_ds2a_in port of the old core.
tx_ds3_anc_in[9:0] I DS3 input after ANC packet insertion. This is the same as the tx_ds1b_in port of the old core.
tx_ds4_anc_in[9:0] I DS4 input after ANC packet insertion. This is the same as the tx_ds2b_in port of the old core.

tx_ds5_anc_in[9:0]

through

tx_ds16_anc_in[9:0]

 I DS5 through DS6 input after ANC packet insertion. The number of these ports that are active depends on the number of data streams being interleaved.
tx_use_anc_in I When Low, the data streams out of the ST 352 packet insertion function are routed internally to the TX output channels. When High, the TX output channels accept data streams from the tx_ds[16:1]_anc_in ports. This is the same as the tx_use_dsin port of the old core.
tx_txdata[19/39:0] O Connect to the TXDATA port of the serial transceiver. The width of this port is control by the DATA_WIDTH parameter and is either 20 or 40-bit.
tx_ce_align_err O This output indicates problems with the 5/6/5/6 clock cycle cadence of the tx_sd_ce input in SD-SDI mode. In SD-SDI mode, the tx_sd_ce signal must follow a regular 5/6/5/6 clock cycle cadence. If it does not, the SD-SDI serial stream is formed incorrectly. The tx_ce_align_err output goes High if the cadence is incorrect. This port is only valid in SD-SDI mode and only if tx_sd_bitrep_bypass is Low.