Simulation of an SDI interface is not typically done on only the SMPTE UHD-SDI core itself, but usually also includes a simulation module of the transceiver plus device-specific logic to control that transceiver and interface it to the SMPTE SD/HD/3G-SDI core. The required transceiver interface and control logic is found in device-specific application notes.
Simulation of the transmit portion of the SMPTE UHD-SDI core requires a source of video providing one or more digital video standards that are supported by the core. The example designs in the device-specific application notes provide video test pattern generators that can provide digital video to the SDI transmitter.
Simulation of the receive portion of the SMPTE UHD-SDI core requires a SDI signal source. The easiest way to provide this the simulation model is with a complete simulation of the SDI transmitter including a video source, the TX portion of the SMPTE UHD-SDI core, and the transceiver simulation model.
To determine if the RX section is correctly receiving the SDI signal, look for pulses on the rx_eav and rx_sav signals at the correct places on each line, absence of pulses on the rx_crc_err_dsN signals, assertion of the rx_mode_locked signal. Verify that the rx_mode output port is indicating the correct SDI mode when rx_mode_locked is asserted. Verify that the video streams output by the receiver match the video streams input to the transmitter, with some amount of latency. Assertion of rx_t_locked takes much longer than assertion of rx_mode_locked because the transport format detector may take up to two frames of video before it can determine the video format, so the format detector outputs (rx_t_locked, rx_t_family, rx_t_rate, and rx_t_scan) are not correct unless the simulation is allowed to run for two full frames of video.