For the transmitter, without using PICXO, different reference clock frequencies are required to transmit the 1000/1000 line rates and the 1000/1001 rates. If both 1000/1000 and 1000/1001 families of rates are to be supported simultaneously, then reference clock frequencies of both 148.5MHz and 148.5/1.001MHz must be available to the PLLs in the quad.
At 12G-SDI line rates, the transmitters can only be clocked by the QPLL. So with 7 series GTX transceivers, as with the RX, it is not possible to have some transmitters running at 11.88 Gb/s and others running at 11.88/1.001 Gb/s in the same quad. In UltraScale/UltraScale+ GTH this restriction does not apply because there are two QPLLs per quad.
Note:
AMD recommends using
a CPLL/QPLL combination with CPLL for TX and QPLL0/1 for RX where both transmit and
receive at 12G-SDI integer and fractional modes are using the same transceiver for
UltraScale+
devices as shown in figure KCU116 Audio Video Loopback Example Design GT Clocking
Architecture in UltraScale/UltraScale+ GTH.