For SD, HD, 3G, and 6G-SDI modes, only a single reference clock frequency is required to receive any supported SDI bit rate. The CDR in the serial transceiver is configured for ±1250 ppm tolerance allowing both bit rates of each SDI standard (such as the HD-SDI bit rates of 1.485 Gb/s and 1.485/1.001 Gb/s, which differ by exactly 1000 ppm) to be received using a single reference clock frequency. Typically, this reference clock frequency is 148.5 MHz.
For 12G-SDI, the serial transceiver CDR does not support ±1250 ppm tolerance. The CDR tolerance is reduced to ±200 ppm at 12G-SDI line rates. This requires different reference clock frequencies to be used to receive 11.88 Gb/s and 11.88/1.001 Gb/s. Typically, the two reference clock frequencies used are 148.5 MHz (to receive 11.88 Gb/s) and 148.5/1.001 MHz (to receive 11.88/1.001 Gb/s).
At 12G-SDI line rates, only the QPLL can be used as the RX clock source. The CPLL cannot be used for 12G-SDI. In the 7 series GTX transceiver quad there is only a single QPLL. Therefore, to switch any receiver in the quad between the 11.88 Gb/s and 11.88/1.001 Gb/s line rates, the reference clock frequency to the QPLL must be dynamically switched between 148.5 MHz and 148.5/1.001 MHz. The implication of this is that it is not possible to have one RX in the GTX quad receiving 11.88 Gb/s while another RX in the same quad is receiving 11.88/1.001 Gb/s.
The AMD UltraScale™ /AMD UltraScale+™ GTH transceiver quad provides more flexibility for 12G-SDI because it has two QPLLs. By supplying one QPLL with a 148.5 MHz reference clock and the other QPLL with a 148.5/1.001 MHz reference clock and, on a per RX basis, selecting which QPLL is used to clock the RX, it is possible to have some receivers in the UltraScale/AMD UltraScale+™ GTH quad receiving 11.88 Gb/s while others are receiving 11.88/1.001 Gb/s.