The 270 Mb/s SD-SDI line rate is too slow to be directly supported by
the serial transceiver transmitters and receivers. To receive SD-SDI, the line rate
of the serial transceiver RX is set to 2.97 Gb/s and it over-samples the incoming
SD-SDI signal by a factor of 11. A data recovery unit, called the NI-DRU, recovers
the actual data from the oversampled data. The NI-DRU generates a data strobe which
runs at a nominal rate of 27 MHz and is asserted with a nominal cadence of 5/6/5/6
RXOUTCLK clock cycles. This data strobe is, therefore, asserted, on average, once
every 5.5 RXOUTCLK cycles. The RXOUTCLK frequency is 148.5 MHz and 148.5 MHz / 5.5 =
27 MHz. The NI-DRU data strobe is output on the rx_ce_out port when the receiver is in SD-SDI mode. When rx_ce_out is High, the data on the output data stream
is valid.
The NI-DRU in the SMPTE UHD-SDI receiver works identically to the NI-DRU used with the older SMPTE UHD-SDI core. For more details about the operation of the NI-DRU and the operation of the SMPTE UHD-SDI RX in SD-SDI mode, see the section entitled SD-SDI Considerations: Receiving SD-SDI in Implementing SMPTE SDI Interfaces with Kintex 7 GTX Transceivers (XAPP592).
It is important to note that the 5/6/5/6 cadence of rx_ce_out can sometimes vary. For example,
occasionally, it can be 5/5/5/6 or 5/6/6/6 or other patterns. This is occurs because
of jitter and because the RX reference clock is not synchronous with the incoming
SD-SDI signal. This is described in more detail in
Implementing SMPTE SDI Interfaces with Kintex 7 GTX
Transceivers (XAPP592).
The following figure is a timing diagram for receiver when running in SD-SDI
mode. It shows the most important timing and data signals. In this example drawing,
rx_ce_out clock enable output is shown with
its typical 5/6/5/6 cycle cadence of the 148.5 MHz rx_usrclk. The received data stream is output on the rx_ds1 port and be captured by downstream modules only
when rx_ce_out is High. The figure shows the
occurrence of the EAV timing signal. The rx_trs
timing output is asserted during all four words of the EAV sequence and the rx_eav output is asserted only during the final word
of the EAV sequence.
For the TX in SD-SDI mode, the application must provide a clock
enable signal to the TX on its tx_sd_ce and
tx_edh_ce inputs that always has exactly a
5/6/5/6 cycle TXOUTCLK cadence. Whenever the tx_sd_ce is High, the SMPTE UHD-SDI TX accepts a 10-bit word on the
single active data stream port. The serial transceiver TX runs at 2.97 Gb/s line
rate and each encoded SD-SDI bit is replicated and sent by the serial transceiver TX
11 times, producing a 270 Mb/s signal.
The following figure show the timing of the essential signals for the
TX in SD-SDI mode. The tx_clk frequency is
148.5 MHz. The tx_sd_ce and tx_edh_ce clock enable inputs must be asserted with a
5/6/5/6 cycle cadence of tx_clk, resulting in a 27
MHz data rate on the tx_ds1_in data stream input.
The tx_ce clock enable input is always High in
this mode. In SD-SDI mode, the tx_line_ch0 input
is only used if ST 352 packets are being inserted. The ST 352 packet insertion
module requires accurate line numbers on the tx_line_ch0 port and the four user data words to be inserted into the
ST 352 packet on the tx_st352_data_ch0 port. The
data on both of these ports must be valid starting at the last word of the EAV
sequence and remaining valid throughout the entire HANC period.