SD-SDI EDH Error Detection - 1.0 English - PG205

The receiver optionally contains an EDH processor that checks the SD-SDI signal for errors. This EDH processor does not update EDH packets in the SD-SDI stream. It simply reports any errors found and also captures the error flags from each EDH packet. The receiver EDH processor can be set to either include in the core or not using the Vivado IDE. The EDH processor has a 16-bit counter which counts the number of fields that have errors. The current error count is output on the rx_edh_errcnt port. The counter can be cleared by asserting rx_edh_clr_errcnt High. You can specify which types of errors are counted using the rx_edh_errcnt_en input port. This port has 16 unary bits which enable and disable 16 different error types. Any bit that is High enables the corresponding error. When this type of error is detected, the error counter increments. Any bit that is Low disables the corresponding error. See Bit Encoding for Error Type shows the encoding of the bits on the rx_edh_errcnt_en port.

The ANC error conditions occur when there are errors in the ancillary data packets. The FF error conditions occur when there are errors in the full field. And, the AP error conditions occur when there are errors in the active portion of the picture. The EDH packet checksum error indicates a checksum error found within the EDH packet itself.

The ANC, FF, and AP error condition sets each have five individual error flags, described below. All flags are asserted High to indicate an error condition. For a complete description of the EDH, EDA, IDH, IDA, and UES error flags in the EDH packet, refer to the SMPTE RP 165 document available from SMPTE.

EDH error

This error condition occurs when the EDH processor detects a CRC error (checksum error for ANC packets) in a field.

EDA error

This error condition occurs when the EDA or EDH flags of the received EDH packet are asserted.

IDH error

This error condition is currently not supported.

IDA error

This error condition occurs when the IDA or IDH flags of the received EDH packet are asserted.

UES error

This error condition occurs when the UES flag in the received EDH packet is asserted.

The actively computed EDH errors for the ANC, AP, and FF are also output on the rx_edh_anc, rx_edh_ap, and rx_edh_ff ports, respectively. Thus, the rx_edh_anc port is asserted whenever a checksum error is detected in an ancillary data packet. The rx_edh_ap port is asserted when the calculated active picture CRC does not match the AP CRC in the EDH packet. And, the rx_edh_ff port is asserted when the calculated full field CRC does not match the FF CRC in the EDH packet.

The EDH processor also outputs the ANC, AP, and FF flags from the EDH packet on the rx_edh_anc_flags, rx_edh_ap_flags, and rx_edh_ff_flags ports, respectively. These output ports are exact copies of the flags found in the last received EDH packet. This means they differ from the actively computed error conditions shown above. For example, the EDH flag (bit 0) of the rx_edh_ap_flags port indicates that the AP EDH flag is set in the last received EDH packet. But, the rx_edh_ap port indicates that the active picture CRC calculated locally by the EDH processor does not match the AP CRC value in the EDH packet. The rx_edh_anc_flags, rx_edh_ap_flags, and rx_edh_ff_flags ports are each 5-bit wide and are encoded as shown in the following table.

The EDH processor also produces four error flags related to the format and contents of the EDH packet. These error flags are output on the rx_edh_packet_flags port. The encoding of this port is shown in the following table.

The TX EDH processor is configured, by default, to always create new EDH packets and insert them whenever the tx_insert_edh input of the top level of the SMPTE UHD-SDI core is High. It generates the new packets without regard to any of the flags located in existing EDH packets. The TX EDH processor does have the capability to inspect incoming EDH packets and change EDH and IDH flags to EDA and IDA flags in the EDH packet. This capability can be enabled by wiring the receive_mode input port of the v_smpte_uhdsdi_edh_processor High. By default, the receive_mode port is wired Low where the EDH processor is instantiated in the v_smpte_uhdsdi_tx module. If the v_smpte_uhdsdi_tx file is edited to wire the receive_mode port of the EDH processor High, the EDH processor then inspects any existing EDH packets and promote an EDH flag in the packet to an EDA flag and promote an IDH flag to an IDA flag.

The RX EDH processor also can be used to change EDH flags to EDA flags and IDH flags to IDA flags. If the RX EDH processor is included in the design, its receive_mode port is wired High. However, the SMPTE UHD-SDI RX does not use the output video stream of the EDH processor which contains the modified EDH packet. If it is necessary for the RX EDH processor to do EDH/IDH flag promotion, then the v_smpte_uhdsdi_rx module needs to be edited to use the data stream on the vid_out port of the EDH processor as the SD-SDI received video stream.