All ports in Table 1 are synchronous with rx_clk.
| Port Name | I/O | Description |
|---|---|---|
| rx_clk | I | Connect to global clock driving the rxusrclk port of the serial transceiver. |
| rx_rst | I | Synchronous reset input. |
| rx_mode_detect_rst | I | Synchronous reset that resets only the SDI mode detect search function. |
| rx_data_in[19/39:0] | I |
Connect to serial transceiver RXDATA port. In SD mode, the NI-DRU data output bus must be connected to the least significant 10-bit of this port (rx_data_in[9:0]). This is different than the older core where the DRU input had a separate input port. Note that in SD, HD, and 3G-SDI modes, the serial transceiver is configured for 20-bit RXDATA port width, but in 6G-SDI and 12G-SDI modes, the serial transceiver is configured for 40-bit RXDATA port width. The RXDATA port width is switched between 20-bit and 40-bit dynamically. When either 6G-SDI or 12G-SDI is supported, the full 40-bit data path between the serial transceiver and the rx_data_in port must be connected. If only 3G-SDI and slower rates are supported, connect the 20-bit RXDATA port of the serial transceiver to rx_data_in[19:0]. |
| rx_sd_data_strobe | I | Connect to the data strobe output of the NI-DRU. |
| rx_frame_en | I | This input enables the SDI framer function. When this input is High, the framer automatically readjusts the output word alignment to match the alignment of each timing reference signal (TRS). TRS is a generic term referring to both EAV and SAV sequences. Normally, this input should be always be High. But, the user application may control this input to implement TRS filtering to prevent a signal misaligned TRS from causing erroneous alignment changes. |
| rx_bit_rate | I |
This input port indicates which bit rate is being received in HD-SDI, 3G-SDI, 6G-SDI, and 12G-SDI modes. This input is only used to generate the value on the rx_t_rate output port, so if the rx_t_rate output port is not used, then it is not required that the rx_bit_rate input be driven. When using the AMD device transceivers, the device-specific transceiver control module contains a bit rate detector that generates the signal to be connected to the rx_bit_rate input port. HD-SDI mode:
3G-SDI mode:
6G-SDI mode:
12G-SDI mode:
|
| rx_mode_enable[5:0] | I |
This port has unary bits to enable reception of each of the five SDI modes: Bit 0 enables HD-SDI mode Bit 1 enables SD-SDI mode Bit 2 enables 3G-SDI mode Bit 3 enables 6G-SDI mode Bit 4 enables 12G-SDI 11.88 Gb/s mode Bit 5 enables 12G-SDI 11.88/1.001 Gb/s mode When a bit is High, the corresponding SDI mode is enabled. When a bit is Low, the receiver does not attempt to detect incoming SDI signals of that mode. Disabling unused SDI modes using these bits decreases the amount of time it takes for the receiver to lock to the incoming signal when it changes modes. Previously this was a 3-bit port, now it is 5-bit to add bits for 12G and 6G. |
| rx_mode_detect_en | I | This port enables the SDI mode detection feature when High. When enabled, the SDI mode detector controls the receiver to search for and lock to the incoming SDI data stream. When disabled, the user application must tell the SDI receiver what SDI mode to operate in using the rx_forced_mode port. |
| rx_forced_mode[2:0] | I |
When the 000 = HD 001 = SD 010 = 3G 100 = 6G 101 = 12G 11.88 Gb/s 110 = 12G 11.88/1.001 Gb/s |
| rx_ready | I | When the rx_ready input is Low, the SDI mode detection function is forced into the unlocked state until rx_ready goes High. This input is used to keep the SDI mode detection function in the unlocked while the serial transceiver is being changed between line rates and reset. Once the serial transceiver has completed its reset cycle, the rx_ready can be asserted High and the SDI mode detection function determines if good data is being received or if the serial transceiver should be changed to another mode. This input is treated as an asynchronous input. |
| rx_mode[2:0] | O |
This output port indicates the current SDI mode of the receiver: 000 = HD 001 = SD 010 = 3G 100 = 6G 101 = 12G 1000/1000 110 = 12G 1000/1001 When the receiver is not locked, the rx_mode port
changes values as the receiver searches for the correct SDI
mode. During this time, the |
| rx_mode_hd | O | High when RX is locked in HD-SDI mode |
| rx_mode_sd | O | High when RX is locked in SD-SDI mode |
| rx_mode_3g | O | High when RX is locked in 3G-SDI mode |
| rx_mode_6g | O | High when RX is locked in 6G-SDI mode |
| rx_mode_12g | O | High when RX is locked in 12G-SDI mode (either bit rate) |
| rx_mode_locked | O |
When this output is Low, the receiver is
actively searching for the SDI mode that matches the input data
stream. During this time, the When the SDI mode detect function is disabled (rx_mode_detect_en = Low), this output is always asserted High. In this case, it is not a reliable indicator of whether or not the SDI receiver is locked to the incoming SDI signal. |
| rx_t_locked | O | This output is High when the transport detection function in the receiver has identified the transport format of the SDI signal. |
| rx_t_family[3:0] | O | This output indicates which family of video signals is being used as
the transport of the SDI interface. This output is only valid when
rx_t_locked is High. This port
does not necessarily identify the video format of the picture being
transported. It only identifies the transport characteristics. See
Video Format Encoding table in Video Format Encoding
for encoding of this port. |
| rx_t_rate[3:0] | O | This output indicates the frame rate of the transport. This is not necessarily the same as the frame rate of the actual picture. This output is only valid when rx_t_locked is High. See Frame Rate Encoding table in Video Format Encoding for details on the encoding of this port. |
| rx_t_scan | O | This output indicates whether the transport is
interlaced (Low) or progressive (High). This is not necessarily the
same as the scan mode of the actual picture. This output is only
valid when rx_t_locked is
High. |
| rx_level_b_3g | O | IN 3G-SDI mode, this output is asserted High when the input signal is level B and Low when it is level A. This output is only valid when rx_mode_3g is High. |
| rx_ce_out[NUM_RX_CE-1:0] | O | This is the RX clock enable output. There are NUM_RX_CE copies of this clock enable on this port. These clock enables are valid in all SDI modes. In SD mode, the CEs have a nominal 5/6/5/6 cadence. In HD and 3GA modes, the CEs are always High. In 3GB mode, the CEs have a 50% duty cycle. In 6G, the duty cycle can by 100% or 50% depending on how may data streams are interleaved onto the signal. In 12G, the duty cycle can be 50% or 25% depending on how many data streams are interleaved onto the signal. This port replaces the rx_ce_sd and rx_dout_rdy_3g ports of the old core and combines their functionality by being correct for all SDI modes. |
| rx_active_streams[2:0] | O |
This port indicates the number of data streams that are active for the current video format being received. The number of active data streams is 2^active_streams. 000: 1 active stream 001: 2 active streams 010: 4 active streams 011: 8 active streams 100: 16 active streams |
| rx_ln_ds<n>[10:0] | O | Captured line number from rx_ds<n>, where <n> is 1 to 16. |
| rx_st352_0[31:0] | O | ST 352 payload ID packet data bytes captured from ds1 |
| rx_st352_0_valid | O | High when rx_st352_0 is valid. |
| rx_st352_1[31:0] | O | The ST 352 payload ID packet data bytes captured from ds3 are output here. In 3G-SDI level A mode, the ST 352 payload ID packet data bytes from ds2 are output here. |
| rx_st352_1_valid | O | High when rx_st352_1 is valid. |
| rx_st352_2[31:0] | O | ST 352 payload ID packet data bytes captured from ds5 |
| rx_st352_2_valid | O | High when rx_st352_2 is valid. |
| rx_st352_3[31:0] | O | ST 352 payload ID packet data bytes captured from ds7 |
| rx_st352_3_valid | O | High when rx_st352_3 is valid. |
| rx_st352_4[31:0] | O | ST 352 payload ID packet data bytes captured from ds9 |
| rx_st352_4_valid | O | High when rx_st352_4 is valid. |
| rx_st352_5[31:0] | O | ST 352 payload ID packet data bytes captured from ds11 |
| rx_st352_5_valid | O | High when rx_st352_5 is valid. |
| rx_st352_6[31:0] | O | ST 352 payload ID packet data bytes captured from ds13 |
| rx_st352_6_valid | O | High when rx_st352_6 is valid. |
| rx_st352_7[31:0] | O | ST 352 payload ID packet data bytes captured from ds15 |
| rx_st352_7_valid | O | High when rx_st352_7 is valid. |
| rx_st352_8[31:0] | O |
ST 352 payload ID packet data bytes captured from ds2
|
| rx_st352_8_valid | O | High when rx_st352_8 is valid. |
| rx_st352_9[31:0] | O | ST 352 payload ID packet data bytes captured from ds4 |
| rx_st352_9_valid | O | High when rx_st352_9 is valid. |
| rx_st352_10[31:0] | O | ST 352 payload ID packet data bytes captured from ds6 |
| rx_st352_10_valid | O | High when rx_st352_10 is valid. |
| rx_st352_11[31:0] | O | ST 352 payload ID packet data bytes captured from ds8 |
| rx_st352_11_valid | O | High when rx_st352_11 is valid. |
| rx_st352_12[31:0] | O | ST 352 payload ID packet data bytes captured from ds10 |
| rx_st352_12_valid | O | High when rx_st352_12 is valid. |
| rx_st352_13[31:0] | O | ST 352 payload ID packet data bytes captured from ds12 |
| rx_st352_13_valid | O | High when rx_st352_13 is valid. |
| rx_st352_14[31:0] | O | ST 352 payload ID packet data bytes captured from ds14 |
| rx_st352_14_valid | O | High when rx_st352_14 is valid. |
| rx_st352_15[31:0] | O | ST 352 payload ID packet data bytes captured from ds16 |
| rx_st352_15_valid | O | High when rx_st352_15 is valid. |
|
rx_crc_err_ds1 to rx_crc_err_ds16 |
O | These 16 ports are the CRC error indicator for each data stream output. When a CRC is detected on a line, the CRC error signal of that data stream becomes asserted starting a few clock cycles after the last CRC word is output on the data stream ports following the EAV that ends the line containing the error. The CRC signal remains asserted for one line time. |
| rx_eav | O | This output is asserted High when the XYZ word of an EAV is present on the data stream output ports. |
| rx_sav | O | This output is asserted High when the XYZ word of a SAV is present on the data stream output ports. |
| rx_trs | O | This output is asserted High while the four consecutive words of any EAV or SAV are present on the data stream output ports, from the 3FF word through the XYZ word. |
| rx_ds1[9:0] | O | Data stream 1 output. In SD mode this is
interleaved Y/C. In HD and 3GA modes, this is the Y channel. In 3GB
mode, this is the link A Y channel. In 6G and 12G modes, this is
ds1. Same as the rx_ds1a output
port of previous core. |
| rx_ds2[9:0] | O | Data stream 2 output. Not used in SD mode. In HD
and 3GA modes, this is the C channel. In 3GB mode, this is the link
A C channel. In 6G and 12G modes, this is ds2. Same as the rx_ds2a port of previous core. |
| rx_ds3[9:0] | O | Data stream 3 output. Not used in SD, HD, and
3GA modes. In 3GB mode, this is the link B Y channel. In 6G and 12G
modes this is ds3. Same as the rx_ds1b port of previous core. |
|
rx_ds4 through rx_ds16[9:0] |
O | Additional data stream output ports. The number of ports that are active depend on the number of data streams interleaved on the SDI signal. These ports are never active in SD, HD, or 3G modes. |
| rx_edh_errcnt_en[15:0] | I | This input controls which EDH error conditions increment the rx_edh_errcnt counter. See Bit
Encoding for Error Type table in SD-SDI EDH Error Detection
for encoding of this port. |
| rx_edh_clr_errcnt | I | When High, this input clears the rx_edh_errcnt counter. This input port
must be High during the same clock cycle when rx_ce_out is also High in order to
clear the error counter. |
| rx_edh_ap | O | This output is asserted High when the active picture CRC calculated for the previous field does not match the AP CRC value in the EDH packet. |
| rx_edh_ff | O | This output is asserted High when the full field CRC calculated for the previous field does not match the FF CRC value in the EDH packet. |
| rx_edh_anc | O | This output is asserted High when an ancillary data packet checksum error is detected. |
| rx_edh_ap_flags[4:0] | O | The active picture error flag bits from the most recently received EDH packet are output on this port. See Bit Encoding for ANC, AP, and FF Error Type table in SD-SDI EDH Error Detection for encoding of this port. |
| rx_edh_ff_flags[4:0] | O | The full frame error flag bits from the most recently received EDH packet are output on this port. See Bit Encoding for ANC, AP, and FF Error Type table in SD-SDI EDH Error Detection for encoding of this port. |
| rx_edh_anc_flags[4:0] | O | The ancillary error flag bits from the most recently received EDH packet are output on this port. See Bit Encoding for ANC, AP, and FF Error Type table in SD-SDI EDH Error Detection for encoding of this port. |
| rx_edh_packet_flags[3:0] | O | This port outputs four error flags related to the most recently received EDH packet. See Bit Encoding for Packet Error Type table in SD-SDI EDH Error Detection for encoding of this port. |
| rx_edh_errcnt[15:0] | O | This is the SD-SDI EDH error counter. It
increments once per field when any of the error conditions enabled
by the rx_edh_err_en port occur
during that field. |