| AMD LogiCORE™ IP Facts Table | |
|---|---|
| Core Specifics | |
| Supported Device Family 1 |
|
| Supported User Interfaces | N/A |
| Resources | Performance and Resource Use web page |
| Provided with Core | |
| Design Files | Verilog source code |
| Example Design |
Implementing SMPTE SDI Interfaces with UltraScale GTH Transceivers (XAPP1248) Implementing SMPTE SDI Interfaces with 7 Series GTX Transceivers (XAPP1249) |
| Test Bench | Verilog |
| Constraints File | XDC |
| Simulation Model | Verilog source HDL |
| Supported S/W Driver 2 | N/A |
| Tested Design Flows 3 | |
| Design Entry | AMD Vivado™ Design Suite |
| Simulation | For supported simulators, see Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973). |
| Synthesis | Vivado Synthesis |
| Support | |
| Release Notes and Known Issues | Master Answer Record: 54547 |
| All Vivado IP Change Logs | Master Vivado IP Change Logs: 72775 |
| Support web page | |
|
|