When a serial transceiver RX or TX is running in HD-SDI mode, the
RXOUTCLK or TXOUTCLK runs at 74.25 MHz (or 74.25/1.001 MHz). In HD-SDI mode, there
are only two 10-bit elementary data streams and the data streams run at the full
clock RXOUTCLK or TXOUTCLK frequency (the rx_ce_out or tx_ce clock enable
signals are always asserted).
The following diagram is a timing diagram for the receiver in HD-SDI mode. The
rx_clk runs at 74.25 MHz (or 74.25/1.001 MHz).
Not shown is the rx_ce_out signal which is always
High in HD-SDI mode. The Y data stream is output on rx_ds1 and the C data stream on rx_ds2. In the following diagram, the EAV sequence is received. The
rx_trs output is asserted High during all four
words of the EAV sequence and the rx_eav signal is
asserted during the fourth word (XYZ word) of the EAV sequence. Captured line
numbers are output on rx_ln_ds1, changing to the
new value immediately after the second LN word is output and remaining unchanged
until the same point of the next line. If a CRC error is detected on one of the data
streams, the corresponding CRC error output becomes asserted two clock cycles after
the second CRC word is output on the data streams and remains asserted until the
same point on the next line.
The following HD-SDI TX Timing Diagram is a timing diagram for the transmitter
in HD-SDI mode. The tx_clk runs at 74.25 MHz (or
74.25/1.001 MHz). The tx_ce input must be asserted
High all of the time. The Y data stream is input on the tx_ds1_in port and the C data stream on the tx_ds2_in port. If the data streams do not already have line numbers
embedded after the EAV, then valid line numbers must be provided on the tx_line_ch0 input port. Line numbers must also be
provided if ST 352 packets are being inserted, even if line numbers are already
embedded in the data streams. The line numbers must be stable on the tx_line_ch0 input port by the same clock cycle in
which the XYZ word of the EAV enters on the data stream inputs. The line number must
remain stable through the duration of the HANC period (until the SAV occurs). If ST
352 packets are to be inserted, then the four user data bytes of the ST 352 packet
must be valid on the tx_sd352_data_ch0 port by the
same clock cycle in which the XYZ word of the EAV enters on the data stream inputs
and must remain stable through the duration of the HANC period.