Dual link and quad link 6G-SDI and 12G-SDI are supported by instantiating two or four SMPTE UHD-SDI cores. In other words, there are two ways to achieve 12G dual link with the core depending on whether there are eight or 16 incoming data streams.
Use Case 1 (12G-8DS)
For each core instance, drive tx_mux_pattern with 3'b010. The tx_ce port must be driven with a 50% duty cycle. Using this setting, the data is output in the following format:
{ds2, ds6, ds4, ds8} when ce is Low
{ds1, ds5, ds3, ds7} when ce is High
Use Case 2 (12G-16DS)
For each core instance, drive tx_mux_pattern with 3'b100. The tx_ce port must be driven with a 25% duty cycle. Using this setting, data is output in the following format:
{ds4, ds12, ds8, ds16} after the rising edge of the clock in which ce is asserted
{ds2, ds10, ds6, ds14} for second clock cycle
{ds3, ds11, ds7, ds15} for third clock cycle
{ds1, ds9, ds5, ds13} for last clock cycle
However, for dual-link HD-SDI, 3G-SDI level B-DL, multi-link 3G-SDI, 6G-SDI, and 12G-SDI, mapping of the video formats to and from elementary data streams is to be done independently outside of the SMPTE UHD-SDI core.
The following requirements must be met:
- tx_mux_pattern 3'b000 requires ce to be asserted all of the time. ds1 passes straight through to output bits [19:10] and ds2 passes through to output bits [9:0].
- tx_mux_pattern 3'b001 requires ce to be asserted with a 50% duty cycle. When ce is Low, {ds2, ds4} is output. When ce is High, {ds1, ds3} is output.
- tx_mux_pattern 3'b010 requires ce to be asserted with a 50% duty cycle. When ce is Low, {ds2, ds6, ds4, ds8} is output. When ce is High, {ds1, ds5, ds3, ds7} is output.
- tx_mux_pattern 3'b011 requires ce to be asserted all of the time. The output is {ds1, ds3, ds2, ds4}.
- tx_mux_pattern 3'b100 requires ce to be asserted 25% of the time. After the rising edge of the clock in which ce is asserted, the output is {ds4, ds12, ds8, ds16}. The next clock cycle the output is {ds2, ds10, ds6, ds14}. The next clock cycle the output is {ds3, ds11, ds7, ds15}. And in the fourth and final clock cycle, the output is {ds1, ds9, ds5, ds13}.