Customizing and Generating the Core - 1.0 English - PG205

SMPTE UHD-SDI LogiCORE IP Product Guide (PG205)
Document ID
PG205
Release Date
2024-06-14
Version
1.0 English

This section includes information about using AMD tools to customize and generate the Core in the AMD Vivado™ Design Suite.

If you are customizing and generating the Core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP Core using the following steps:

  1. Select the IP from the IP catalog.
  2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.

Figure 1. SMPTE UHD-SDI Vivado IDE (7 Series Speed Grade 1 and 2)
Figure 2. SMPTE UHD-SDI Vivado IDE (7 Series Speed Grade 3 and UltraScale/UltraScale+)

The Vivado IDE displays a representation of the IP symbol on the left side and the parameter assignments on the right, as follows:

Component Name
The base name of output files generated for the module. Names must begin with a letter and must be composed of characters a to z, 0 to 9 and "_". The name v_smpte_uhdsdi_v1_0 cannot be used as a component name.
Maximum Line Rate
Specifies the maximum rate supported for that device family.

For 7 series speed grade 3 and AMD UltraScale™ /AMD UltraScale+™ devices, the following line rate are supported:

  • 3G SDI
  • 6G SDI
  • 12G SDI 8 Data Stream
  • 12G SDI 16 Data Stream

For 7 series speed grade, grade 1 and 2 devices, the following line rate are supported:

  • 3G SDI
  • 6G SDI
Include RX EDH Processor
If this parameter is ENABLED, then the EDH processor for the receiver section of the SMPTE UHD-SDI core is included. If this parameter is DISABLED, then the EDH processor for the receiver section is not included.
Insert ST352 in C-stream
If this parameter is enabled, St352 payload packets are inserted into the C channel of the data streams.