Core Parameters - 1.0 English - PG205

The core has three parameters:

INCLUDE_RX_EDH_PROCESSOR

When this parameter is TRUE, the RX section includes an EDH processor for error detection in SD-SDI mode. When this parameter is FALSE, the EDH processor is not included in the RX section.

DATA_WIDTH

This parameter specifies the rx_data_in and tx_txdata port widths. The only permitted values for this parameter are 20 and 40. When only using SD, HD, and 3G modes, the DATA_WIDTH parameter should be set to 20. However, when using 6G or 12G modes, DATA_WIDTH must be set to 40. Note that this is a static parameter, it only specifies the width of these ports. If DATA_WIDTH is 40, the actual data width used changes dynamically based on the current SDI modes of the RX and TX.

NUM_RX_CE

This parameter specifies the number of identical copies of the RX clock enable signal are present on the rx_ce_out port. The minimum value permitted is 1, in which case the rx_ce_out port is 1 bit wide.