Constraining the Core - 1.0 English

Required Constraints

The period of the rx_clk and tx_clk must be constrained depending on the maximum line rate to be supported.

The EDH processors in the design also need multi cycle clock path constraints which are automatically provided when the core is generated.

Device, Package, and Speed Grade Selections

For 7 series devices, -3 speed grade parts are required to support 12G-SDI. Not all packages support 12G-SDI line rates. The MGTAVCC voltage rail must be set to 1.05 V if 12G-SDI operation is required. This voltage level also support s the other SDI lines rates. If the maximum line rate is 6G-SDI or slower, then -1 speed grade devices are sufficient and the MGTAVCC voltage rail can be set to the normal value of 1.00 V.

UltraScale/UltraScale+ GTH transceivers support operation at all SDI rates up to and including 12G-SDI in -1 speed grade devices.

Clock Frequencies

Applications that support 12G-SDI operation must constrain the frequency of the SMPTE UHD-SDI core rx_clk and tx_clk to 297 MHz. The source of the rx_clk is usually the serial transceiver signal, RXOUTCLK. The source of the tx_clk is usually the serial transceiver signal, TXOUTCLK. The exact constraints to be used on these clocks depends on the hierarchical structure of the design, but they are similar to the constraints shown below with an application specific path to the TXOUTCLK and RXOUTCLK pins of the serial transceiver.

create_clock -period 3.333 -name tx0_outclk -waveform {0.000 1.667} [get_pins SDI/GTX/gtxe2_i/TXOUTCLK]
create_clock -period 3.333 -name rx0_outclk -waveform {0.000 1.667} [get_pins SDI/GTX/gtxe2_i/RXOUTCLK]

When the maximum line rate is 6G-SDI or slower, the maximum clock frequency of rx_clk and tx_clk is 148.5 MHz and the following constraints are appropriate:

create_clock -period 6.667 -name tx0_outclk -waveform {0.000 3.333} [get_pins SDI/GTX/gtxe2_i/TXOUTCLK]
create_clock -period 6.667 -name rx0_outclk -waveform {0.000 3.333} [get_pins SDI/GTX/gtxe2_i/RXOUTCLK]