A complete SDI interface is comprised of:
- A multi-Gigabit transceiver (such as AMD 7 series GTX, AMD UltraScale™ GTH, or AMD UltraScale+™ GTH)
- The SMPTE UHD-SDI IP core
- Control logic for the transceiver Third-party SDI cable driver and cable equalizer to interface the transceiver to the SDI cable
- Transceiver reference clock sources
The following figure shows the high-level block diagram of an SDI receive/transmit interface using the SMPTE UHD-SDI core. In this figure, the blocks shaded grey are external to the FPGA, everything else is contained within the FPGA. The SMPTE UHD-SDI core implements one SDI receiver and one SDI transmitter. If only a receiver or only a transmitter is needed by the application, the input ports for the unused half of the core can be tied to ground, and the output ports left unconnected. The synthesis tool optimizes the unused portion of the core out of the application.
When both the receiver and transmitter sections of the SMPTE UHD-SDI core are used, the receiver and transmitter are completely independent. They can be operating in different SDI modes and line rates.
The SMPTE UHD-SDI core can be generated in 20-bit mode in which case it only supports SD, HD, and 3G-SDI modes. Or, it can be generated in 40-bit mode in which case it supports all SDI mode from SD-SDI through 12G-SDI.