The next case occurs when 12G-SDI and all lower rates must be supported and when only one 12G-SDI line rate, but not both, needs to be supported.
In this case, shown in the following figure, the QPLL is given a single reference clock frequency, which can be either 148.5 MHz or 148.5/1.001 MHz, depending on which 12G-SDI line rate is to be supported (148.5 MHz for 11.88 Gb/s or 148.5/1.001 MHz for 11.88/1.001 Gb/s). In the example shown in the figure, the quad is only supports 11.88 Gb/s, so the reference clock frequency is 148.5 MHz. The QPLL operates in range 2 at 11.88 GHz and provides a 5.94 GHz clock to each RX and TX unit in the quad.
The CPLLs are all given a 148.5/1.001 MHz reference clock and operate at 2.97/1.001 GHz, providing a clock of that frequency to the RX and TX of the associated transceiver.
Any RX or TX in the quad running at 11.88 Gb/s must use the QPLL clock as its serial clock source and must have is PLL divider set to divide by 1. At 6G-SDI rates, the RX can use either the QPLL or the CPLL as long as the correct divider value is used (divide by 1 when using the CPLL and divide by 2 when using the QPLL). At 3G-SDI rates and lower, the RX must use the CPLL. The TX units uses the QPLL when transmitting integer frame rate SDI line rates and the CPLL when transmitting non-integer frame rate SDI lines rates. In this scenario, the only limitation is that only the 11.88 Gb/s 12G-SDI line rate is supported. It is not possible to transmit or receive at 11.88/1.001 Gb/s given the arrangement of the reference clocks.
If the QPLL is given the 148.5/1.001 MHz reference clock and the CPLL is given the 148.5 MHz reference clock, then the application can support the 11.88/1.001 Gb/s line rate, but not the 11.88 Gb/s line rate. All slower line rates can be supported.