In 6G-SDI mode, the RXOUTCLK/TXOUTCLK frequency is 148.5 MHz (or 148.5/1.001
MHz). Depending on the 6G-SDI mapping mode used, there can be either four or eight
active data streams. When four data streams are active, these data streams run at
the full RXOUTCLK/TXOUTCLK frequency (rx_ce_out
and tx_ce signals are always High). When eight
data streams are active, these data streams run at half the RXOUTCLK/TXOUTCLK
frequency and the rx_ce_out and tx_ce signals are asserted every other clock cycle
(50% duty cycle).
The following 6G-SDI RX 4-way Interleave Timing Diagram is a timing diagram
of the receiver running in 6G-SDI mode receiving a signal containing four data
streams. The rx_clk frequency is 148.5 MHz or
148.5/1.001 MHz. The rx_ce_out output is always
High. The four received data streams are output on rx_ds1 through rx_ds4. The diagram
shows the EAV being received and the rx_trs and
rx_eav behave the same as with other SDI
standards. Line numbers are captured from all four data streams and output on
rx_ln_ds1 through rx_ln_ds4. CRC errors are detected individually for all four data
streams and indicated on the rx_crc_err_ds1
through rx_crc_err_ds4 outputs.
The following 6G-SDI RX 8-way Interleave Timing Diagram is a timing diagram
for the receiver in 6G-SDI mode when receiving a signal containing eight data
streams. The rx_clk frequency is 148.5 MHz or
148.5/1.001 MHz. The rx_ce_out signal is asserted
every other clock cycle. The eight received data streams are output on rx_ds1 through rx_ds8. The diagram shows the EAV being received and the rx_trs and rx_eav
behave the same as with other SDI standards. Line numbers are captured from all
eight data streams and output on rx_ln_ds1 through
rx_ln_ds8. CRC errors are detected
individually for all eight data streams and indicated on the rx_crc_err_ds1 through rx_crc_err_ds8 outputs.
The following 6G-SDI TX 4-way Interleave Timing Diagram is a timing diagram
for the transmitter in 6G-SDI mode when transmitting a signal containing four data
streams. The tx_clk frequency is 148.5 MHz or
148.5/1.001 MHz. The tx_ce input must be High all
of the time. The four data streams being transmitted must be on tx_ds1_in through tx_ds4_in. Line numbers supplied on
-
tx_line_ch0are inserted into data streams 1 and 2 -
tx_line_ch1are inserted into data streams 3 and 4.
Line numbers must also be supplied on tx_line_ch0 and tx_line_ch1 in order
for ST 352 packet insertion to function. If ST 352 packet insertion is enabled, for
Y-stream (by default), the user data words for the ST 352 packets inserted into
- data stream 1 must be supplied on
tx_st352_data_ch0 - data stream 3 must be supplied on
tx_st352_data_ch1.
You must supply the tx_st352_data_ch0_c and tx_st352_data_ch1_c signals for ST 352 insertion into the
C-stream.
The following 6G-SDI TX 8-way Interleave Timing Diagram is a timing diagram
for the transmitter in 6G-SDI mode when transmitting a signal containing eight data
streams. The tx_clk frequency is 148.5 MHz or
148.5/1.001 MHz. The tx_ce input must be asserted
every other clock cycle. The eight data streams being transmitted must be on tx_ds1_in through tx_ds8_in. Line numbers supplied on
-
tx_line_ch0are inserted into data streams 1 and 2 -
tx_line_ch1are inserted into data streams 3 and 4 -
tx_line_ch2are inserted into data streams 5 and 6 -
tx_line_ch4
Line numbers must also be supplied on tx_line_ch0 through tx_line_ch4 in
order for ST 352 packet insertion to function. If ST 352 packet insertion is enabled
(through a port), the user data words for the ST 352 packets inserted into
- data stream 1 must be supplied on
tx_st352_data_ch0 - data stream 3 must be supplied on
tx_st352_data_ch1 - data stream 5 must be supplied on
tx_st352_data_ch2 - data stream 7 must be supplied on
tx_st352_data_ch3.