In 3G-SDI mode, the RXOUTCLK/TXOUTCLK frequency is 148.5 MHz (or
148.5/1.001 MHz). In 3G-SDI level A mode, there are two 10-bit elementary data
streams and these data streams run at the full RXOUTCLK/TXOUTCLK frequency (the
rx_ce_out or tx_ce clock enable signals are always asserted). However, in level B
mode, there are four 10-bit elementary data streams active. In level B mode, the
clock enables (rx_ce_out and tx_ce) are asserted every other clock cycle (50% duty
cycle).
The following is the timing diagram for the receiver in 3G-SDI level A mode.
In this case, a 1080p 50 or 60 Hz image is being received. The rx_clk is running at 148.5 MHz (or 148.5/1.001 MHz).
The rx_ce_out is always High. The Y data stream is
output on rx_ds1 and the C data stream on rx_ds2. The timing of the other signals shown is
identical to that described for HD-SDI receiver. Two line number outputs, rx_ln_ds1 and rx_ln_ds2, and two CRC error outputs, rx_crc_err_ds1 and rx_crc_err_ds2,
are active.
The following 3G-SDI Level B RX Timing Diagram is a timing diagram for the
receiver in 3G-SDI level B mode. The rx_clk runs
at 148.5 MHz or 148.5/1.001 MHz. The rx_ce_out
signal is asserted every other clock cycle. Four elementary streams are received, a
Y and a C data stream for Link A on rx_ds1 and
rx_ds2 and a Y and a C data stream for Link B
on rx_ds3 and rx_ds4. The rx_trs signal is
asserted as all four words of the EAV are output on the data stream ports. The
rx_eav output is asserted when the XYZ word of
the EAV is output. Four line number output ports, rx_ln_ds1 through rx_ln_ds4, are
active. Line numbers change immediately after the second LN word is output on the
data stream ports.
The following 3G-SDI Level A TX Timing Diagram is a timing diagram for the
transmitter in 3G-SDI level A mode. The tx_clk
runs at 148.5 MHz (or 148.5/1.001 MHz). The tx_ce
input must be asserted High all of the time. In this example, a 1080p 50 or 60 Hz
image is being transmitted. The Y data stream enters on tx_ds1_in and the C data stream on tx_ds2_in. If the data streams do not already have line numbers
embedded after the EAV, then valid line numbers must be provided on the tx_line_ch0 input port. Line numbers must also be
provided if ST 352 packets are being inserted, even if line numbers are already
embedded in the data streams. The line numbers must be stable on the tx_line_ch0 input port by the same clock cycle in
which the XYZ word of the EAV enters on the data stream inputs. The line number must
remain stable through the duration of the HANC period (until the SAV occurs).
If ST 352 packets are to be inserted, then the four user data bytes
of the ST 352 packets for data stream 1 must be valid on the tx_sd352_data_ch0 port by the same clock cycle in
which the XYZ word of the EAV enters on the data stream inputs and must remain
stable through the duration of the HANC period. The four user data bytes for the ST
352 packets inserted into data stream 2 must be supplied on tx_st352_data_ch1.
The following 3G-SDI Level B TX Timing Diagram is a timing diagram for the
transmitter in 3G-SDI level B mode. The tx_clk
runs at 148.5 MHz or 148.5/1.001 MHz. The tx_ce
input must be asserted every other clock cycle. Four data stream inputs, tx_ds1_in through tx_ds4_in, are active. Data is captured on these data stream input
ports on the rising edge of tx_clk when tx_ce is High. Line numbers supplied on
-
tx_line_ch0are inserted into data streams 1 and 2 -
tx_line_ch1are inserted into data streams 3 and 4.
Line numbers must also be supplied on tx_line_ch0 and tx_line_ch1 in order
for ST 352 packet insertion to function. If ST 352 packet insertion is enabled
(through a port), the user data words for the ST 352 packets inserted into data
stream 1 must be supplied on tx_st352_data_ch0 and
the user data words for the ST 352 packets inserted into data stream 3 must be
supplied on tx_st352_data_ch1. If Insert ST352 in
C-Stream is enabled, the user data words for the ST 352 packets inserted into
- data stream 2 must be supplied on
tx_st352_data_ch0_c - data stream 4 must be supplied on
tx_st352_data_ch1_c.