In 12G-SDI mode, the RXOUTCLK/TXOUTCLK frequency is 297 MHz (or
297/1.001 MHz). Depending on the 12G-SDI mapping mode used, there may be either
eight or sixteen active elementary data streams. When eight elementary data streams
are active, the data streams run at half the RXOUTCLK/TXOUTCLK frequency and the
rx_ce_out and tx_ce have 50% duty cycles. When sixteen elementary data streams are
active, the data streams run at one quarter the RXOUTCLK/TXOUTCLK frequency and the
rx_ce_out and tx_ce have 25% duty cycles.
The timing diagram for 8-way interleave on a 12G-SDI RX interface is
identical to Figure 4 , the 8-way interleave 6G-SDI RX
interface with the exception that rx_clk run at
297 MHz for 12G-SDI.
The following is a timing diagram for the receiver in 12G-SDI mode when
receiving a signal containing sixteen data streams. The rx_clk frequency is 297 MHz or 297/1.001 MHz. The rx_ce_out signal is asserted one clock cycle out of
every four (25% duty cycle). The sixteen received data streams are output on rx_ds1 through rx_ds16. Not all sixteen data streams are shown in the diagram, but
they are all active. The following diagram shows the EAV being received and the
rx_trs and rx_eav behave the same as with other SDI standards. Line numbers are
captured from all sixteen data streams and output on rx_ln_ds1 through rx_ln_ds16. CRC
errors are detected individually for all sixteen data streams and indicated on the
rx_crc_err_ds1 through rx_crc_err_ds16
outputs. The line number and CRC error outputs are not shown on the timing diagram,
but their timing is the same as with other SDI modes relative to the position of the
EAV and LN words in the data streams.
The timing diagram for 12G-SDI TX with eight interleaved data streams is
identical to the above diagram, the 8-way interleaved 6G-SDI transmitter timing
diagram, except that the tx_clk frequency is 297
MHz.
The following diagram is a timing diagram for the transmitter in 12G-SDI mode
when transmitting a signal containing sixteen data streams. The tx_clk frequency is 297 MHz or 297/1.001 MHz. The
tx_ce input must be asserted every other clock
cycle. The sixteen data streams being transmitted must be on tx_ds1_in through tx_ds16_in. When either line number insertion or ST 352 packet
insertion is enabled (through the tx_insert_ln
port), line numbers must be supplied on the eight line number input ports tx_line_ch0 through tx_line_ch7. There is one line number input port for each pair of data
streams. The line number on tx_line_ch0 are
associated with data streams tx_ds1_in and tx_ds2_in, tx_line_ch1 with tx_ds3_in and
tx_ds4_in, and so on. As with the other SDI
modes, the line number values on the line number inputs must be stable by the rising
edge of the tx_clk on which the XYZ words of
the EAVs enter the data stream input ports and must remain stable until the
beginning of the SAV, in other words, for the duration of the HANC interval on each
line. If ST 352 packet insertion is enabled, the line numbers must be supplied to
the transmitter as just described and the user data words for the ST 352 packets
must also be supplied on the tx_st352_data_ch0
through tx_st352_data_ch7 input ports. There
is one ST 352 user data input port for each pair of data streams. ST 352 packets are
only inserted into the odd numbered data stream of each pair (the Y data stream).
The ST 352 data supplied on tx_st352_data_ch0
is associated with data stream 1 (tx_ds1_in ),
tx_st352_data_ch1 is associated with data
stream 3 (tx_ds3_in ), and so on. The data on
these ST 352 data input ports must meet the same timing requirements as the line
numbers. You can insert ST3 52 into the C data stream, shown in the waveform. You
must supply the ST 352 payload on tx_st352_data_ch0_c to tx_st352_data_ch7_c, depending on the available data streams.