User State Machine - 3.1 English - PG203

The read and write through the AXI4-Lite slave module interface is controlled by a state machine as shown in the following figure.

Figure 1. User State Machine for AXI4-Lite Interface

Following is the functional description of each state.

IDLE_STATE

By default the FSM will be in the IDLE_STATE state. When the user_read_req signal becomes High, then it moves to READ_STATE; else if the user_write_req signal is High, it moves to the WRITE_STATE; else it remains in IDLE_STATE.

WRITE_STATE

You provide S_AXI_AWVALID, S_AXI_AWADDR, S_AXI_WVALID, S_AXI_WDATA and S_AXI_WSTRB in this state to write to the register map through AXI. When S_AXI_BVALID and S_AXI_BREADY from the AXI slave are High then it moves to ACK_STATE. If there is any write operation than happens in any illegal addresses, the S_AXI_BRESP[1:0] indicates 2'b10 that asserts the write error signal.

READ_STATE

You provide S_AXI_ARVALID and S_AXI_ARADDR in this state to read from the register map through AXI. When S_AXI_RVALID and S_AXI_RREADY are High then it moves to ACK_STATE. If there is any read operation that occurs from any illegal addresses, the S_AXI_RRESP[1:0] indicates 2'b10 that asserts the read error signal

ACK_STATE

The state moves to IDLE_STATE.