The user side interface of the UltraScale Devices Integrated 100G Ethernet subsystem is a simple packet interface referred to as the LBUS. The LBUS interface implemented in the 100G Ethernet subsystem is 512-bits segmented.
The LBUS consists of three separate interfaces:
- Transmitter (TX) interface
- Receiver (RX) interface
- Status/Control interface
The transmitter accepts packet-oriented data, packages the data in accordance with the IEEE 802.3 Specification and sends that packaged data to the serial transceiver interface. The transmitter has control/configuration inputs to shape the data packaging to meet design-specific requirements.
The receiver accepts IEEE 802.3 data streams from the serial transceiver interface and provides packet-oriented data to the user side.
The status/control interface is used to set the characteristics of the interface and monitor its operation.
The 100G Ethernet subsystem employs a segmented LBUS interface to prevent the loss of potential bandwidth that occurs at the end of a packet when the size of the packet is not a multiple of the LBUS width.
The segmented LBUS is a collection of narrower LBUSs, each 128 bits wide, with multiple transfers presented in parallel during the same clock cycle. Each segment has all the control signals associated with a complete 128-bit LBUS. The 512-bit segmented LBUS has four 128-bit segments with the signals for each segment shown in the following table .
| Segment Number | TX Signals | RX Signals |
|---|---|---|
| 0 |
tx_datain0[127:0] tx_enain0 tx_sopin0 tx_eopin0 tx_errin0 tx_mtyin0[3:0] |
rx_dataout0[127:0] rx_enaout0 rx_sopout0 rx_eopout0 rx_errout0 rx_mtyout0[3:0] |
| 1 |
tx_datain1[127:0] tx_enain1 tx_sopin1 tx_eopin1 tx_errin1 tx_mtyin1[3:0] |
rx_dataout1[127:0] rx_enaout1 rx_sopout1 rx_eopout1 rx_errout1 rx_mtyout1[3:0] |
| 2 |
tx_datain2[127:0] tx_enain2 tx_sopin2 tx_eopin2 tx_errin2 tx_mtyin2[3:0] |
rx_dataout2[127:0] rx_enaout2 rx_sopout2 rx_eopout2 rx_errout2 rx_mtyout2[3:0] |
| 3 |
tx_datain3[127:0] tx_enain3 tx_sopin3 tx_eopin3 tx_errin3 tx_mtyin3[3:0] |
rx_dataout3[127:0] rx_enaout3 rx_sopout3 rx_eopout3 rx_errout3 rx_mtyout3[3:0] |
The transmit and receive signals are defined as follows:
-
tx_datain0[127:0] - Transmit LBUS Data. This bus receives input data from the user logic. The value of the
bus is captured in every cycle for which
tx_enainis sampled as 1. -
tx_datain0[127:0] - Transmit LBUS Data. This bus receives input data from the user logic. The value of the
bus is captured in every cycle for which
tx_enainis sampled as 1. -
tx_datain0[127:0] - Transmit LBUS Data. This bus receives input data from the user logic. The value of the
bus is captured in every cycle for which
tx_enainis sampled as 1. -
tx_enain0 - Transmit LBUS Enable. This signal is used to enable the TX LBUS Interface. All signals
on the LBUS interface are sampled only in cycles during which
tx_enainis sampled as 1. -
tx_sopin0 - Transmit LBUS Start Of Packet. This signal is used to indicate the Start Of Packet (SOP)
when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is
sampled only in cycles during which
tx_enainis sampled as 1. -
tx_eopin0 - Transmit LBUS End Of Packet. This signal is used to indicate the EOP when it is sampled
as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in
cycles during which
tx_enainis sampled as 1. -
tx_errin0 - Transmit LBUS Error. This signal is used to indicate that a packet contains an error
when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is
sampled only in cycles during which
tx_enainandtx_eopinare sampled as 1. -
tx_mtyin0[3:0] - : Transmit LBUS Empty. This bus is used to indicate how many bytes of the
tx_datainbus are empty or invalid for the last transfer of the current packet. This bus is sampled only in cycles thattx_enainandtx_eopinare sampled as 1.When
tx_eopinandtx_errinare sampled as 1, the value oftx_mtyin[2:0]is ignored and treated as if it is 000. The other bits oftx_mtyinare used as usual. -
rx_dataout0[127:0] - Receive LBUS Data. The value of the bus is only valid in cycles during which
rx_enaoutis sampled as 1. -
rx_enaout0 - Receive LBUS Enable. This signal qualifies the other signal of the RX LBUS Interface.
Signals of the RX LBUS Interface are only valid in cycles during which
rx_enaoutis sampled as 1. -
rx_sopout0 - Receive LBUS SOP. This signal indicates the SOP when it is sampled as 1 and is only
valid in cycles during which
rx_enaoutis sampled as a 1. -
rx_sopout0 - Receive LBUS SOP. This signal indicates the SOP when it is sampled as 1 and is only
valid in cycles during which
rx_enaoutis sampled as a 1. -
rx_eopout0 - Receive LBUS EOP. This signal indicates the EOP when it is sampled as 1 and is only
valid in cycles during which
rx_enaoutis sampled as a 1. -
rx_errout0 - Receive LBUS Error. This signal indicates that the current packet being received has an
error when it is sampled as 1. This signal is only valid in cycles when both
rx_enaoutandrx_eopoutare sampled as a 1. When this signal is 0, it indicates that there is no error in the packet being received. -
rx_mtyout0[3:0] - Receive LBUS Empty. This bus indicates how many bytes of the
rx_dataoutbus are empty or invalid for the last transfer of the current packet. This bus is only valid in cycles when bothrx_enaoutandrx_eopoutare sampled as 1.When
rx_erroutandrx_enaoutare sampled as 1, the value ofrx_mtyout[2:0]is always 000. Other bits ofrx_mtyoutare as usual.
The transmitter accepts packet-oriented data. The transmitter has control/configuration inputs to shape the data packaging to meet design-specific requirements. The receiver accepts Ethernet bitstreams from the SerDes and provides packet-oriented data to the user side segmented LBUS.