The following figures show timing diagram waveforms for the AXI4-Lite interface.
- Valid Write transactions (Figure 1)
- Invalid Write transactions (Figure 2)
- Valid Read transactions (Figure 3)
- Invalid Read transactions (Figure 4)
Figure 1. AXI4-Lite User Side Write Transaction
Figure 2. AXI4-Lite User Side Write Transaction with Invalid Write
Address
Figure 3. AXI4-Lite User Side Read Transaction
Figure 4. AXI4-Lite User Side Read Transaction with Invalid Read Address
