Transcode Bypass Mode Ports - 3.1 English - PG203

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)

Document ID: PG203
Release Date: 2024-07-17
Version: 3.1 English

The following table lists the RS-FEC ports that are used for data transfer in transcode bypass mode only.

Table 1. Transcode Bypass Mode Ports
Name	I/O	Clock Domain	Description
rsfec_bypass_rx_din[329:0]	I	rx_clk	Data input to RS decoder.
rsfec_bypass_rx_din_cw_start	I	rx_clk	When high, indicates that current data word on rsfec_bypass_rx_din is the first in an RS codeword.
rsfec_bypass_tx_din[329:0]	I	tx_clk	Data input to RS encoder.
rsfec_bypass_tx_din_cw_start	I	tx_clk	When high, indicates that current data word on rsfec_bypass_tx_din is the first in an RS codeword.
rsfec_bypass_rx_dout[329:0]	O	rx_clk	Data output from RS decoder.
rsfec_bypass_rx_dout_cw_start	O	rx_clk	When high, indicates that current data word on rsfec_bypass_rx_dout is the first in a decoded RS codeword.
rsfec_bypass_rx_dout_valid	O	rx_clk	When high, indicates that the current data word on rsfec_bypass_rx_dout is valid.
rsfec_bypass_tx_dout[329:0]	O	tx_clk	Data output from RS encoder.
rsfec_bypass_tx_dout_cw_start	O	tx_clk	When high, indicates that current data word on rsfec_bypass_tx_dout is the first in an encoded RS codeword.
rsfec_bypass_tx_dout_valid	O	tx_clk	When high, indicates that the current data word on rsfec_bypass_tx_dout is valid.