TX LBUS Interface - 3.1 English - PG203

The synchronous TX Local bus interface accepts packet-oriented data of arbitrary length. All signals are synchronous relative to the rising-edge of the clk port. The following figure shows a sample waveform for data transactions for two consecutive 65-byte packets using a 512-bit segmented bus. Each of the four segments is 128 bits wide.

TX Transactions

Data is written into the interface on every clock cycle when tx_enain is asserted. This signal qualifies the other inputs of the TX Local bus interface. This signal must be valid every clock cycle. When tx_enain is deasserted, data on the other buses is ignored.

The start of a packet is identified by asserting tx_sopin with tx_enain. The end of a packet is identified by asserting tx_eopin with tx_enain. Both tx_sopin and tx_eopin can be asserted during the same cycle provided there are no empty segments between them. This is done for packets that are less than or equal to the bus width.

Data is presented on the tx_datain inputs. For a given segment, the first byte of the packet is written on bits [127:120], the second byte on bits [119:112], and so forth.

For a 128-bit segment, the first 16 bytes of a packet are presented on the bus during the cycle that tx_sopin and tx_enain are asserted. Subsequent 16-byte chunks are written during successive cycles with tx_sopin negated. The last bytes of the packet are written with tx_eopin asserted. Unless tx_eopin is asserted, all 128 bits must be presented with valid data whenever tx_enain is asserted.

During the last cycle of a packet, the tx_mtyin signals might be asserted. The value of tx_mtyin must be 0 for all but the last cycle. The tx_mtyin signals indicate how many byte lanes in the data bus are invalid (or empty). The tx_mtyin signals only have meaning during cycles when both tx_enain and tx_eopin are asserted. For a 128-bit wide segment, tx_mtyin is 4 bits wide.

If tx_mtyin has a value of 0x0, there are no empty byte lanes, or in other words, all bits of the data bus are valid. If tx_mtyin has a value of 0x1, then the 1-byte lane is empty. Specifically bits [7:0] of tx_datain do not contain valid data. If tx_mtyin has a value of 0x2, then the 2-byte lanes are empty. Specifically bits [15:0] do not contain valid data. If tx_mtyin has a value of 0x3, then 3-byte lanes are empty, and specifically bits [23:0] do not contain valid data This pattern continues until 15 of 16 bytes are invalid or empty. The following table shows the relation of tx_mtyin and empty byte lanes.

During the last cycle of a packet, when tx_eopin is asserted with tx_enain, tx_errin might also be asserted. This marks the packet as being in error, and it is dropped (that is, not transmitted). When tx_errin is asserted, the value of tx_mtyin is ignored.

tx_rdyout

Data can be safely written, that is, tx_enain asserted, when tx_rdyout is asserted. After tx_rdyout is negated, additional writes using tx_enain can be safely performed provided tx_ovfout is never asserted. When tx_rdyout is asserted again, additional data can be written. If at any time the back-pressure mechanism is violated, the tx_ovfout is asserted to indicate the violation. Up to four write cycles might be safely performed after tx_rdyout is negated, but no more until tx_rdyout is asserted again.