TX LBUS Interface - 3.1 English - PG203

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)

Document ID
PG203
Release Date
2025-12-17
Version
3.1 English

The synchronous TX Local bus interface accepts packet-oriented data of an arbitrary length. All signals are synchronous relative to the rising-edge of the clk port. The following figure shows a sample waveform for data transactions for two consecutive 65-byte packets using a 512-bit segmented bus. Each of the four segments is 128-bits wide.

Figure 1. Transmit Timing Diagram