Subsystem Overview - 3.1 English - PG203

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)

Document ID
PG203
Release Date
2024-07-17
Version
3.1 English

This product guide describes the function and operation of the AMD UltraScale+™ devices Integrated 100G Ethernet subsystem, including how to design, customize, and implement it.

The core is designed to the IEEE std 802.3-2012 (https://standards.ieee.org/ieee/802.3/5084) specification with an option for IEEE 1588-2008 (http://standards.ieee.org/findstds/standard/1588-2008.html) hardware timestamping. The core instantiates the UltraScale+ Devices Integrated Block for 100G Ethernet. This core simplifies the design process and reduces time to market.

Although the core is a fully-verified solution, implementing a complete design varies depending on the configuration and functionality of the application. See Product Specification for details about the core.

Important: CAUI-4 and switchable CAUI-10/CAUI-4/100GAUI-4 require GTY transceivers. 100GAUI-2 mode configuration requires GTM transceivers.