Status and Statistics Register Space - 3.1 English - PG203

The status and statistics registers indicate the health of the link and histograms counters to provide classification of the traffic and error counts. The status and counters are all read-only.

Status registers are cleared on read and counters are controlled by a "tick" mechanism.

Some bits are sticky, that is, latching their values High or Low after being set. This is indicated by the suffix LH (Latched High) or LL (Latched Low).

• R/LL: Register bit defaults to 1, upon error condition this bit latches to 0, the bit is set back to its default state after each read.
• R/LH: Register bit defaults to 0, upon error condition this bit latches to 1, the bit is set back to its default state after each read.
• If the register bit does not default to its respective values after each read, the error state is ongoing.

The counters accumulate their counts in an internal accumulator. A write to the TICK_REG register (or the input port pm_tick is 1'b1) causes the accumulated counts to be pushed to the readable STAT_*_MSB/LSB registers and simultaneously clears the accumulators. The STAT_*_MSB/LSB registers can then be read. In this way all values stored in the statistics counters represent a snapshot over the same time-interval.

The STAT_CYCLE_COUNT_MSB/LSB register contains a count of the number of SerDes clock cycles between TICK_REG register writes. This allows for easy time-interval based statistics. The counters have a default width of 48 bits. The counters saturate to 1s. The values in the counters are held until the next write to the TICK_REG register.

The addresses shown in the following table for the counters are the addresses of the LSB register or bits 31:0 of the count. The MSB bits 47:32 of the counter are located at +0x4 from the LSB.