Register Descriptions - 3.1 English - PG203

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)
Document ID
PG203
Release Date
2025-12-17
Version
3.1 English
Table 1. GT_RESET_REG
Address Bits Default Type Description
0x0000 0 0 RW gt_reset_all. A write of 1 issues a RESET to the GT. This is a clear on write register
31:1 0 NA Reserved
Table 2. RESET_REG
Address Bits Default Type Description
0x0004 9:0 0 RW

usr_rx_serdes_reset. Unused PCS bits are RESERVED.

A write of 1 in a given bit location puts that PCS lane logic into reset.
27:10 0 NA Reserved
28 0 RW

ctl_an_reset. A write of 1, issues a reset to the Auto-Negotiation module. This is a clear on write register.

Note: This register bit is available when 'Include AN/LT Logic' option is selected in the GUI.
29 0 NA Reserved
30 0 RW usr_rx_reset. RX core reset. A write of 1 puts the RX path in reset
31 0 RW usr_tx_reset. TX core reset. A write of 1 puts the TX path in reset
Table 3. SWITCH_CORE_MODE_REG
Address Bits Default Type Description
0x0008 0 0 RW

For Runtime Switch mode only.

A write of 1 enables the mode switch between CAUI10 and CAUI4. This is a clear on write register.

This is an input to the trans debug module that performs the GT DRP operations.
31:1 0 NA Reserved
Table 4. CONFIGURATION_TX_REG1
Address Bits Default Type Description
0x000C 0 0 RW ctl_tx_enable
2:1 0 NA Reserved
3 0 RW ctl_tx_send_lfi
4 0 RW ctl_tx_send_rfi
5 0 RW ctl_tx_send_idle
15:6 0 NA Reserved
16 0 RW ctl_tx_test_pattern
31:17 0 NA Reserved
Table 5. CONFIGURATION_RX_REG1
Address Bits Default Type Description
0x0014 0 0 RW ctl_rx_enable
6:1 0 NA Reserved
7 0 RW ctl_rx_force_resync
8 0 RW ctl_rx_test_pattern
31:9 0 NA Reserved
Table 6. CORE_MODE_REG
Address Bits Default Type Description
0x0020 1:0 1 R

Core mode register:

  • 2'b00: CAUI10
  • 2'b01: CAUI4
  • 2'b10: Runtime Switchable CAUI10
  • 2'b11: Runtime Switchable CAUI4
31:2 0 NA Reserved
  1. Based on core configuration.
Table 7. CORE_VERSION_REG
Address Bits Default Type Description
0x0024 7:0 minor R

Current version of the core in the format “major.minor”

For example core version 1.7

Bits [7:0] represents minor version that is 7

Bits [15:8] represents major version that is 1
15:8 major R
31:16 0 NA Reserved
Table 8. CONFIGURATION_TX_BIP_OVERRIDE
Address Bits Default Type Description
0x002C 7:0 0 RW ctl_tx_lane0_vlm_bip7_override_value
8 0 RW ctl_tx_lane0_vlm_bip7_override
31:9 0 NA Reserved
Table 9. CONFIGURATION_TX_FLOW_CONTROL_CONTROL_REG1
Address Bits Default Type Description
0x0030 8:0 0 RW ctl_tx_pause_enable
31:9 0 NA Reserved
Table 10. CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG1
Address Bits Default Type Description
0x0034 15:0 0 RW ctl_tx_pause_refresh_timer0
31:16 0 RW ctl_tx_pause_refresh_timer1
Table 11. CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG2
Address Bits Default Type Description
0x0038 15:0 0 RW ctl_tx_pause_refresh_timer2
31:16 0 RW ctl_tx_pause_refresh_timer3
Table 12. CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG3
Address Bits Default Type Description
0x003C 15:0 0 RW ctl_tx_pause_refresh_timer4
31:16 0 RW ctl_tx_pause_refresh_timer5
Table 13. CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG4
Address Bits Default Type Description
0x0040 15:0 0 RW ctl_tx_pause_refresh_timer6
31:16 0 RW ctl_tx_pause_refresh_timer7
Table 14. CONFIGURATION_TX_FLOW_CONTROL_REFRESH_REG5
Address Bits Default Type Description
0x0044 15:0 0 RW ctl_tx_pause_refresh_timer8
31:16 0 NA Reserved
Table 15. CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG1
Address Bits Default Type Description
0x0048 15:0 0 RW ctl_tx_pause_quanta0
31:16 0 RW ctl_tx_pause_quanta1
Table 16. CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG2
Address Bits Default Type Description
0x004C 15:0 0 RW ctl_tx_pause_quanta2
31:16 0 RW ctl_tx_pause_quanta3
Table 17. CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG3
Address Bits Default Type Description
0x0050 15:0 0 RW ctl_tx_pause_quanta4
31:16 0 RW ctl_tx_pause_quanta5
Table 18. CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG4
Address Bits Default Type Description
0x0054 15:0 0 RW ctl_tx_pause_quanta6
31:16 0 RW ctl_tx_pause_quanta7
Table 19. CONFIGURATION_TX_FLOW_CONTROL_QUANTA_REG5
Address Bits Default Type Description
0x0058 15:0 0 RW ctl_tx_pause_quanta8
31:16 0 NA Reserved
Table 20. CONFIGURATION_TX_OTN_PKT_LEN_REG
Address Bits Default Type Description
0x005C 7:0 0 RW ctl_tx_min_packet_len
22:8 0 RW ctl_tx_max_packet_len
31:23 0 NA Reserved
Table 21. CONFIGURATION_TX_OTN_CTL_REG
Address Bits Default Type Description
0x0060 0 0 RW ctl_tx_check_sfd
1 0 RW ctl_tx_check_preamble
2 0 RW ctl_tx_ignore_fcs
31:3 0 NA Reserved
Table 22. CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG1
Address Bits Default Type Description
0x0084 8:0 0 RW ctl_rx_pause_enable
9 0 NA Reserved
10 0 RW ctl_rx_enable_gcp
11 0 RW ctl_rx_enable_pcp
12 0 RW ctl_rx_enable_gpp
13 0 RW ctl_rx_enable_ppp
14 0 NA Reserved
23:15 0 RW ctl_rx_pause_ack
31:24 0 NA Reserved
Table 23. CONFIGURATION_RX_FLOW_CONTROL_CONTROL_REG2
Address Bits Default Type Description
0x0088 0 0 RW ctl_rx_check_mcast_gcp
1 0 RW ctl_rx_check_ucast_gcp
2 0 RW ctl_rx_check_sa_gcp
3 0 RW ctl_rx_check_etype_gcp
4 0 RW ctl_rx_check_opcode_gcp
5 0 RW ctl_rx_check_mcast_pcp
6 0 RW ctl_rx_check_ucast_pcp
7 0 RW ctl_rx_check_sa_pcp
8 0 RW ctl_rx_check_etype_pcp
9 0 RW ctl_rx_check_opcode_pcp
10 0 RW ctl_rx_check_mcast_gpp
11 0 RW ctl_rx_check_ucast_gpp
12 0 RW ctl_rx_check_sa_gpp
13 0 RW ctl_rx_check_etype_gpp
14 0 RW ctl_rx_check_opcode_gpp
15 0 RW ctl_rx_check_opcode_ppp
16 0 RW ctl_rx_check_mcast_ppp
17 0 RW ctl_rx_check_ucast_ppp
18 0 RW ctl_rx_check_sa_ppp
19 0 RW ctl_rx_check_etype_ppp
31:20 0 NA Reserved
Table 24. GT_LOOPBACK_REG
Address Bits Default Type Description
0x0090 0 0 RW

ctl_gt_loopback

0 is for Normal operation (external loopback).

1 is for Near End PMA loopback (internal loopback).
31:1 0 NA Reserved
Table 25. CONFIGURATION_AN_CONTROL_REG1
Address Bits Default Type Description
0x00A0 0 0 RW ctl_autoneg_enable
1 1 RW ctl_autoneg_bypass 1
9:2 0 RW ctl_an_nonce_seed
10 0 RW ctl_an_pseudo_sel
11 0 RW ctl_restart_negotiation
12 0 RW ctl_an_local_fault
31:13 0 NA Reserved
  1. For simulation, the ctl_autoneg_bypass value is written as 1 during reset. To test with ANLT enabled configuration, write the register with ctl_autoneg_enable to 1 and ctl_autoneg_bypass to 0.
Table 26. CONFIGURATION_AN_CONTROL_REG2
Address Bits Default Type Description
0x00A4 0 0 RW ctl_an_pause
1 0 RW ctl_an_asmdir
17:2 0 NA Reserved
18 0 RW ctl_an_cl91_fec_request
19 0 RW ctl_an_cl91_fec_ability
20 0 RW ctl_an_fec_25g_rs_request
21 0 NA Reserved
22 0 RW ctl_an_loc_np
23 0 RW ctl_an_lp_np_ack
31:24 0 NA Reserved
Table 27. CONFIGURATION_AN_ABILITY
Address Bits Default Type Description
0x00A8 0 0 RW ctl_an_ability_1000base_kx
1 0 RW ctl_an_ability_10gbase_kx4
2 0 RW ctl_an_ability_10gbase_kr
3 0 RW ctl_an_ability_40gbase_kr4
4 0 RW ctl_an_ability_40gbase_cr4
5 0 RW ctl_an_ability_100gbase_cr10
6 0 RW ctl_an_ability_100gbase_kp4
7 0 RW ctl_an_ability_100gbase_kr4
8 0 RW ctl_an_ability_100gbase_cr4
9 0 RW ctl_an_ability_25gbase_krcr_s
10 0 RW ctl_an_ability_25gbase_krcr
11 0 RW ctl_an_ability_2_5gbase_kx
12 0 RW ctl_an_ability_5gbase_kr
13 0 RW ctl_an_ability_50gbase_krcr
14 0 RW ctl_an_ability_100gbase_kr2cr2
15 0 RW ctl_an_ability_200gbase_kr4cr4
16 0 RW ctl_an_ability_25gbase_kr1
17 0 RW ctl_an_ability_25gbase_cr1
18 0 RW ctl_an_ability_50gbase_kr2
19 0 RW ctl_an_ability_50gbase_cr2
31:20 0 NA Reserved
Table 28. CONFIGURATION_LT_CONTROL_REG1
Address Bits Default Type Description
0x00AC 0 0 RW ctl_lt_training_enable
1 0 RW ctl_lt_restart_training
31:2 0 NA Reserved
Table 29. CONFIGURATION_LT_TRAINED_REG
Address Bits Default Type Description
0x00B0 3:0 0 RW ctl_lt_rx_trained
31:4 0 NA Reserved
Table 30. CONFIGURATION_LT_PRESET_REG
Address Bits Default Type Description
0x00B4 3:0 0 RW ctl_lt_preset_to_tx
31:4 0 NA Reserved
Table 31. CONFIGURATION_LT_INIT_REG
Address Bits Default Type Description
0x00B8 3:0 0 RW ctl_lt_initialize_to_tx
31:4 0 NA Reserved
Table 32. CONFIGURATION_LT_SEED_REG0
Address Bits Default Type Description
0x00BC 10:0 0 RW ctl_lt_pseudo_seed0
26:16 0 RW ctl_lt_pseudo_seed1
31:27 0 NA Reserved
Table 33. CONFIGURATION_LT_SEED_REG1
Address Bits Default Type Description
0x00C0 10:0 0 RW ctl_lt_pseudo_seed2
26:16 0 RW ctl_lt_pseudo_seed3
31:27 0 NA Reserved
Table 34. CONFIGURATION_LT_COEFFICIENT_REG0
Address Bits Default Type Description
0x00C4 1:0 0 RW ctl_lt_k_p1_to_tx0
3:2 0 RW ctl_lt_k0_to_tx0
5:4 0 RW ctl_lt_k_m1_to_tx0
7:6 0 RW ctl_lt_stat_p1_to_tx0
9:8 0 RW ctl_lt_stat0_to_tx0
11:10 0 RW ctl_lt_stat_m1_to_tx0
17:16 0 RW ctl_lt_k_p1_to_tx1
19:18 0 RW ctl_lt_k0_to_tx1
21:20 0 RW ctl_lt_k_m1_to_tx1
23:22 0 RW ctl_lt_stat_p1_to_tx1
25:24 0 RW ctl_lt_stat0_to_tx1
27:26 0 RW ctl_lt_stat_m1_to_tx1
31:28 0 NA Reserved
Table 35. CONFIGURATION_LT_COEFFICIENT_REG1
Address Bits Default Type Description
0x00C8 1:0 0 RW ctl_lt_k_p1_to_tx2
3:2 0 RW ctl_lt_k0_to_tx2
5:4 0 RW ctl_lt_k_m1_to_tx2
7:6 0 RW ctl_lt_stat_p1_to_tx2
9:8 0 RW ctl_lt_stat0_to_tx2
11:10 0 RW ctl_lt_stat_m1_to_tx2
17:16 0 RW ctl_lt_k_p1_to_tx3
19:18 0 RW ctl_lt_k0_to_tx3
21:20 0 RW ctl_lt_k_m1_to_tx3
23:22 0 RW ctl_lt_stat_p1_to_tx3
25:24 0 RW ctl_lt_stat0_to_tx3
27:26 0 RW ctl_lt_stat_m1_to_tx3
31:28 0 NA Reserved
Table 36. USER_REG0
Address Bits Default Type Description
0x00CC 31:0 0 RW user_reg0
Table 37. RSFEC_CONFIG_INDICATION_CORRECTION
Address Bits Default Type Description
0x1000 0 0 RW ctl_rx_rsfec_enable_correction
1 0 RW ctl_rx_rsfec_enable_indication
2 0 RW ctl_rx_rsfec_ieee_error_indication_mode
31:3 0 NA Reserved
Table 38. RSFEC_CONFIG_ENABLE
Address Bits Default Type Description
0x107C 0 0 RW ctl_rx_rsfec_enable
1 0 RW

ctl_tx_rsfec_enable, when Enable TX OTN Interface option is deselected and Include IEEE 802.3bj RS-FEC option is selected, or

ctl_rsfec_enable, when Enable TX OTN Interface option is selected and Include IEEE 802.3bj RS-FEC option is selected.
31:2 0 NA Reserved
Table 39. STAT_TX_STATUS_REG
Address Bits Default Type Description
0x0200 0 0 R/LH stat_tx_local_fault
31:1 0 NA Reserved
Table 40. STAT_RX_STATUS_REG
Address Bits Default Type Description
0x0204 0 1 R/LL stat_rx_status
1 1 R/LL stat_rx_aligned
2 0 R/LH stat_rx_misaligned
3 0 R/LH stat_rx_aligned_err
4 0 R/LH stat_rx_hi_ber
5 0 R/LH stat_rx_remote_fault
6 0 R/LH stat_rx_local_fault
7 0 R/LH stat_rx_internal_local_fault
8 0 R/LH stat_rx_received_local_fault
11:9 0 R/LH stat_rx_test_pattern_mismatch
12 0 R/LH stat_rx_bad_preamble
13 0 R/LH stat_rx_bad_sfd
14 0 R/LH stat_rx_got_signal_os
31:15 0 NA Reserved
Table 41. STAT_STATUS_REG1
Address Bits Default Type Description
0x0208 3:0 0 NA Reserved
4 0 R/LH stat_tx_ptp_fifo_read_error
5 0 R/LH stat_tx_ptp_fifo_write_error
31:6 0 NA Reserved
Table 42. STAT_RX_BLOCK_LOCK_REG
Address Bits Default Type Description
0x020C 19:0 1 R/LL stat_rx_block_lock
31:20 0 NA Reserved
Table 43. STAT_RX_LANE_SYNC_REG
Address Bits Default Type Description
0x0210 19:0 1 R/LL stat_rx_synced
31:20 0 NA Reserved
Table 44. STAT_RX_LANE_SYNC_ERR_REG
Address Bits Default Type Description
0x0214 19:0 0 R/LH stat_rx_synced_err
31:20 0 NA Reserved
Table 45. STAT_RX_LANE_AM_ERR_REG
Address Bits Default Type Description
0x0218 19:0 0 R/LH stat_rx_mf_err
31:20 0 NA Reserved
Table 46. STAT_RX_LANE_AM_LEN_ERR_REG
Address Bits Default Type Description
0x021C 19:0 0 R/LH stat_rx_mf_len_err
31:20 0 NA Reserved
Table 47. STAT_RX_LANE_AM_REPEAT_ERR_REG
Address Bits Default Type Description
0x0220 19:0 0 R/LH stat_rx_mf_repeat_err
31:20 0 NA Reserved
Table 48. STAT_RX_PCSL_DEMUXED_REG
Address Bits Default Type Description
0x0224 19:0 0 R stat_rx_pcsl_demuxed
31:20 0 NA Reserved
Table 49. STAT_RX_PCS_LANE_NUM_REG1
Address Bits Default Type Description
0x0228 4:0 0 R stat_rx_pcsl_number_0
9:5 0 R stat_rx_pcsl_number_1
14:10 0 R stat_rx_pcsl_number_2
19:15 0 R stat_rx_pcsl_number_3
24:20 0 R stat_rx_pcsl_number_4
29:25 0 R stat_rx_pcsl_number_5
31:30 0 NA Reserved
Table 50. STAT_RX_PCS_LANE_NUM_REG2
Address Bits Default Type Description
0x022C 4:0 0 R stat_rx_pcsl_number_6
9:5 0 R stat_rx_pcsl_number_7
14:10 0 R stat_rx_pcsl_number_8
19:15 0 R stat_rx_pcsl_number_9
24:20 0 R stat_rx_pcsl_number_10
29:25 0 R stat_rx_pcsl_number_11
31:30 0 NA Reserved
Table 51. STAT_RX_PCS_LANE_NUM_REG3
Address Bits Default Type Description
0x0230 4:0 0 R stat_rx_pcsl_number_12
9:5 0 R stat_rx_pcsl_number_13
14:10 0 R stat_rx_pcsl_number_14
19:15 0 R stat_rx_pcsl_number_15
24:20 0 R stat_rx_pcsl_number_16
29:25 0 R stat_rx_pcsl_number_17
31:30 0 NA Reserved
Table 52. STAT_RX_PCS_LANE_NUM_REG4
Address Bits Default Type Description
0x0234 4:0 0 R stat_rx_pcsl_number_18
9:5 0 R stat_rx_pcsl_number_19
31:10 0 NA Reserved
Table 53. STAT_RX_BIP_OVERRIDE_REG
Address Bits Default Type Description
0x0238 7:0 0 R stat_rx_lane0_vlm_bip7
8 0 R stat_rx_lane0_vlm_bip7_valid
31:9 0 NA Reserved
Table 54. STAT_TX_OTN_STATUS_REG
Address Bits Default Type Description
0x023C 0 0 R/LH stat_tx_remote_fault
1 0 R/LH stat_tx_internal_local_fault
2 0 R/LH stat_tx_received_local_fault
5:3 0 R/LH stat_tx_test_pattern_mismatch
6 0 R/LH stat_tx_bad_preamble
7 0 R/LH stat_tx_bad_sfd
8 0 R/LH stat_tx_got_signal_os
31:9 0 NA Reserved
Table 55. STAT_AN_STATUS_REG
Address Bits Default Type Description
0x0258 0 0 R stat_an_fec_enable
1 0 R stat_an_rs_fec_enable
2 0 R stat_an_autoneg_complete
3 0 R stat_an_parallel_detection_fault
4 0 R stat_an_tx_pause_enable
5 0 R stat_an_rx_pause_enable
6 0 R/LH stat_an_lp_ability_valid
7 0 R stat_an_lp_autoneg_able
8 0 R stat_an_lp_pause
9 0 R stat_an_lp_asm_dir
10 0 R stat_an_lp_rf
11 0 R stat_an_lp_fec_10g_ability
12 0 R stat_an_lp_fec_10g_request
13 0 R/LH stat_an_lp_extended_ability_valid
17:14 0 R stat_an_lp_ability_extended_fec
18 0 R stat_an_lp_fec_25g_rs_request
19 0 R stat_an_lp_fec_25g_baser_request
31:20 0 NA Reserved
Table 56. STAT_AN_ABILITY_REG
Address Bits Default Type Description
0x025C 0 0 R stat_an_lp_ability_1000base_kx
1 0 R stat_an_lp_ability_10gbase_kx4
2 0 R stat_an_lp_ability_10gbase_kr
3 0 R stat_an_lp_ability_40gbase_kr4
4 0 R stat_an_lp_ability_40gbase_cr4
5 0 R stat_an_lp_ability_100gbase_cr10
6 0 R stat_an_lp_ability_100gbase_kp4
7 0 R stat_an_lp_ability_100gbase_kr4
8 0 R stat_an_lp_ability_100gbase_cr4
9 0 R stat_an_lp_ability_25gbase_krcr_s
10 0 R stat_an_lp_ability_25gbase_krcr
11 0 R stat_an_lp_ability_2_5gbase_kx
12 0 R stat_an_lp_ability_5gbase_kr
13 0 R stat_an_lp_ability_50gbase_krcr
14 0 R stat_an_lp_ability_100gbase_kr2cr2
15 0 RW stat_an_lp_ability_200gbase_kr4cr4
16 0 RW stat_an_lp_ability_25gbase_kr1
17 0 RW stat_an_lp_ability_25gbase_cr1
18 0 RW stat_an_lp_ability_50gbase_kr2
19 0 RW stat_an_lp_ability_50gbase_cr2
31:20 0 NA Reserved
Table 57. STAT_AN_LINK_CTL_REG_1
Address Bits Default Type Description
0x0260 1:0 0 R stat_an_link_cntl_1000base_kx
3:2 0 R stat_an_link_cntl_10gbase_kx4
5:4 0 R stat_an_link_cntl_10gbase_kr
7:6 0 R stat_an_link_cntl_40gbase_kr4
9:8 0 R stat_an_link_cntl_40gbase_cr4
11:10 0 R stat_an_link_cntl_100gbase_cr10
13:12 0 R stat_an_link_cntl_100gbase_kp4
15:14 0 R stat_an_link_cntl_100gbase_kr4
17:16 0 R stat_an_link_cntl_100gbase_cr4
19:18 0 R stat_an_link_cntl_25gbase_krcr_s
21:20 0 R stat_an_link_cntl_25gbase_krcr
23:22 0 R stat_an_link_cntl_2_5gbase_kx
25:24 0 R stat_an_link_cntl_5gbase_kr
27:26 0 R stat_an_link_cntl_50gbase_krcr
29:28 0 R stat_an_link_cntl_100gbase_kr2cr2
31:30 0 R stat_an_link_cntl_200gbase_kr4cr4
Table 58. STAT_LT_STATUS_REG1
Address Bits Default Type Description
0x0264 3:0 0 R stat_lt_initialize_from_rx
19:16 0 R stat_lt_preset_from_rx
31:20 0 R Reserved
Table 59. STAT_LT_STATUS_REG2
Address Bits Default Type Description
0x0268 3:0 0 R stat_lt_training
19:16 0 R stat_lt_frame_lock
31:20 0 R Reserved
Table 60. STAT_LT_STATUS_REG3
Address Bits Default Type Description
0x026C 3:0 0 R stat_lt_signal_detect
19:16 0 R stat_lt_training_fail
31:20 0 R Reserved
Table 61. STAT_LT_STATUS_REG4
Address Bits Default Type Description
0x0270 3:0 0 R stat_lt_rx_sof
31:4 0 R Reserved
Table 62. STAT_LT_COEFFICIENT0_REG
Address Bits Default Type Description
0x0274 1:0 0 R stat_lt_k_p1_from_rx0
3:2 0 R stat_lt_k0_from_rx0
5:4 0 R stat_lt_k_m1_from_rx0
7:6 0 R stat_lt_stat_p1_from_rx0
9:8 0 R stat_lt_stat0_from_rx0
11:10 0 R stat_lt_stat_m1_from_rx0
17:16 0 R stat_lt_k_p1_from_rx1
19:18 0 R stat_lt_k0_from_rx1
21:20 0 R stat_lt_k_m1_from_rx1
23:22 0 R stat_lt_stat_p1_from_rx1
25:24 0 R stat_lt_stat0_from_rx1
27:26 0 R stat_lt_stat_m1_from_rx1
31:28 0 NA Reserved
Table 63. STAT_LT_COEFFICIENT1_REG
Address Bits Default Type Description
0x0278 1:0 0 R stat_lt_k_p1_from_rx2
3:2 0 R stat_lt_k0_from_rx2
5:4 0 R stat_lt_k_m1_from_rx2
7:6 0 R stat_lt_stat_p1_from_rx2
9:8 0 R stat_lt_stat0_from_rx2
11:10 0 R stat_lt_stat_m1_from_rx2
17:16 0 R stat_lt_k_p1_from_rx3
19:18 0 R stat_lt_k0_from_rx3
21:20 0 R stat_lt_k_m1_from_rx3
23:22 0 R stat_lt_stat_p1_from_rx3
25:24 0 R stat_lt_stat0_from_rx3
27:26 0 R stat_lt_stat_m1_from_rx3
31:28 0 NA Reserved
Table 64. STAT_AN_LINK_CTL_REG_2
Address Bits Default Type Description
0x027C 1:0 0 R stat_an_link_cntl_25gbase_kr1
3:2 0 R stat_an_link_cntl_25gbase_cr1
5:4 0 R stat_an_link_cntl_50gbase_kr2
7:6 0 R stat_an_link_cntl_50gbase_cr2
31:8 0 NA Reserved
Table 65. STAT_RSFEC_STATUS_REG
Address Bits Default Type Description
0x1004 1:0 0 NA Reserved
2 0 R stat_rx_rsfec_hi_ser
3 0 R stat_rx_rsfec_hi_ser_lh
7:4 0 NA Reserved
8 0 R stat_rx_rsfec_am_lock0
9 0 R stat_rx_rsfec_am_lock1
10 0 R stat_rx_rsfec_am_lock2
11 0 R stat_rx_rsfec_am_lock3
13:12 0 NA Reserved
14 0 R stat_rx_rsfec_lane_alignment_status
31:15 0 NA Reserved
Table 66. STAT_RSFEC_LANE_MAPPING_REG
Address Bits Default Type Description
0x1018 1:0 0 R stat_rx_rsfec_lane_mapping0
3:2 0 R stat_rx_rsfec_lane_mapping1
5:4 0 R stat_rx_rsfec_lane_mapping2
7:6 0 R stat_rx_rsfec_lane_mapping3
31:8 0 NA Reserved
Table 67. STAT_TX_OTN_RSFEC_STATUS_REG
Address Bits Default Type Description
0x1044 0 1 R/LL stat_tx_rsfec_block_lock
1 1 R/LL stat_tx_rsfec_am_lock
2 1 R/LL stat_tx_rsfec_lane_alignment_status
31:3 0 NA Reserved
Table 68. TICK_REG
Address Bits Default Type Description
0x02B0 0 0 WO/SC tick_reg. Writing a 1 to the Tick bit will trigger a snapshot of all the Statistics counters into their readable registers. The bit self-clears, thus only a single write is required by the user
31:1 0 NA Reserved