Product Specification - 3.1 English

Product Specification - 3.1 English - PG203

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)

Document ID

PG203

Release Date

2025-12-17

Version

3.1 English

The following table defines the integrated CMAC block for the 100 Gb/s Ethernet solution.

Table 1. Integrated CMAC Block for the 100 Gb/s Ethernet Solution
Protocol	Lane Width	Line Rate	SerDes	SerDes Width
CAUI-10	x10	10.3125 Gb/s	GTH GTY	32b
CAUI-4	x4	25.78125 Gb/s³	GTY GTM	With GTY: 80b With GTM: 64b
Runtime Switchable CAUI-4/CAUI-10	CAUI-10: x10 CAUI-4: x4	CAUI-10: 10.3125 Gb/s CAUI-4: 25.78125 Gb/s	GTY ¹	CAUI-10: 32b CAUI-4: 80b
100GAUI-2	x2	53.125 Gb/s²	GTM	160b
100GAUI-4	x4	26.5625 Gb/s	GTY⁴ GTM	With GTY: 80b With GTM: 64b
CAUI-4 requires GTY or GTM transceivers which are available in select devices. Runtime switchable CAU-10/CAUI-4 require GTY transceivers available only in select devices. The line rate of 53.125 Gb/s (GTM transceivers) is available on select devices. The line rate of 25.78125 Gb/s is available on select devices,Virtex UltraScale devices in typical speed grades. 100GAUI-4 requires GTY or GTM transceivers which are available in select devices.

The subsystem instantiates the CMAC block along with the necessary GTH or GTY transceivers. The subsystem provides an example of how the two blocks are connected together, along with the reset and clocking for those blocks.

The integrated block is designed to IEEE std 802.3-2012.

The following figure illustrates the described interfaces to the integrated CMAC block.

Serial transceiver interface
User-side transmit and receive LBUS or AXIS interface
Pause processing
IEEE 1588-2008 timestamping interface
Status/Control interface
Dynamic reconfiguration port (DRP) interface used for configuration
RS-FEC IP Block

Figure 1. Integrated CMAC Block for 100 Gb/s Ethernet