Port Descriptions - Port Descriptions - 3.1 English - PG203

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)
Document_ID
PG203
Release_Date
2025-12-17
Version
3.1 English

The following table lists the additional signals present on the core for the OTN Interface feature. OTN_LANES is the number of data words on the OTN interface and is equal to 5.

Table 1. Additional Signals for the OTN Interface
OTN Interface – RX Path
rx_otn_clk I

Optional. RX clock for the OTN interface clock. Should be tied to rx_clk.

  • Using a clock other than rx_clk will incur extra output FIFOing logic and resources.
rx_otn_ena O Indicates that the data on the rx_otn_data_* buses are valid.
rx_otn_lane0 O A 1 on this signal indicates that the data word for PCS lane 0 is present on rx_otn_data_0.
rx_otn_vlmarker O A 1 on this signal indicates that the data on rx_otn_data_* buses are the alignment marker words.
rx_otn_data_{0:OTN_LANES-1}[65:0] O

Data output for the receive datapath.

[65:64] = sync header

[63:0] = data
rx_otn_bip8_{0:OTN_LANES-1}[7:0] O Optional. Recalculated BIP values.