Port Descriptions - 3.1 English - PG203

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)
Document ID
PG203
Release Date
2025-12-17
Version
3.1 English

The following table provides a detailed description of the Integrated 100G Ethernet ports. See CORE XCI Top Level Port List for ports at the XCI level of the subsystem.

Important: 100GAUI-2 mode requires devices with GTM transceivers that run at 53.125 Gb/s. CAUI-4 mode requires GTY or GTM (with lesser speed that is, 25.78125 Gb/s) in the select devices. Runtime switchable CAUI-10/CAUI-4 modes require devices with GTY transceivers that run at 25.78125 Gb/s.
Table 1. Transceiver I/O
Name I/O Domain Description
RX_SERDES_ALT_DATA0[15:0] I RX_SERDES_CLK[0] 16-bit group of the Receive data bus from SerDes0. There are 10 RX_SERDES_DATA buses; one bus for each SerDes lane, and each bus has either 80 or 32 bits depending on whether operation is in CAUI-4 or CAUI-10 mode respectively. The first four SerDes lanes can operate at 80 bits or 32 bits, and the remaining six lanes operate at 32 bits. The 32 LSBs of the first four lanes are used in CAUI-10 mode. The mapping of the 80 bits, comprised of a 16-bit group and a 64-bit group, is not obvious. See PCS Lane Multiplexing for details.
RX_SERDES_ALT_DATA1[15:0] I RX_SERDES_CLK[1] 16-bit group of the Receive data bus from SerDes1.
RX_SERDES_ALT_DATA2[15:0] I RX_SERDES_CLK[2] 16-bit group of the Receive data bus from SerDes2.
RX_SERDES_ALT_DATA3[15:0] I RX_SERDES_CLK[3] 16-bit group of the Receive data bus from SerDes3.
RX_SERDES_DATA0[63:0] I RX_SERDES_CLK[0] 64-bit group of the Receive data bus from SerDes0
RX_SERDES_DATA1[63:0] I RX_SERDES_CLK[1] 64-bit group of the Receive data bus from SerDes1.
RX_SERDES_DATA2[63:0] I RX_SERDES_CLK[2] 64-bit group of the Receive data bus from SerDes2.
RX_SERDES_DATA3[63:0] I RX_SERDES_CLK[3] 64-bit group of the Receive data bus from SerDes3.
RX_SERDES_DATA4[31:0] I RX_SERDES_CLK[4] Data bus from SerDes4.
RX_SERDES_DATA5[31:0] I RX_SERDES_CLK[5] Data bus from SerDes5.
RX_SERDES_DATA6[31:0] I RX_SERDES_CLK[6] Data bus from SerDes6.
RX_SERDES_DATA7[31:0] I RX_SERDES_CLK[7] Data bus from SerDes7.
RX_SERDES_DATA8[31:0] I RX_SERDES_CLK[8] Data bus from SerDes8.
RX_SERDES_DATA9[31:0] I RX_SERDES_CLK[9] Data bus from SerDes9.
TX_SERDES_ALT_DATA0[15:0] O TX_SERDES_CLK[0] 16-bit group of the Transmit data bus to SerDes0. There are 10 TX_SERDES_DATA buses; one bus for each SerDes lane, and each bus has either 80 or 32 bits depending on whether the operation is in CAUI-4 or CAUI-10 mode respectively. The first four SerDes lanes can operate at 80 bits or 32 bits, and the remaining six lanes operate at 32 bits. The 32 LSBs of the first four lanes are used in CAUI-10 mode. The mapping of the 80 bits, comprised of a 16-bit group and a 64-bit group, is not obvious. See PCS Lane Multiplexing for details.
TX_SERDES_ALT_DATA1[15:0] O TX_SERDES_CLK[1] 16-bit group of the Transmit data bus to SerDes1.
TX_SERDES_ALT_DATA2[15:0] O TX_SERDES_CLK[2] 16-bit group of the Transmit data bus to SerDes2.
TX_SERDES_ALT_DATA3[15:0] O TX_SERDES_CLK[3] 16-bit group of the Transmit data bus to SerDes3.
TX_SERDES_DATA0[63:0] O TX_SERDES_CLK[0] 64-bit group of the Transmit data bus to SerDes0.
TX_SERDES_DATA1[63:0] O TX_SERDES_CLK[1] 64-bit group of the Transmit data bus to SerDes1.
TX_SERDES_DATA2[63:0] O TX_SERDES_CLK[2] 64-bit group of the Transmit data bus to SerDes2.
TX_SERDES_DATA3[63:0] O TX_SERDES_CLK[3] 64-bit group of the Transmit data bus to SerDes3.
TX_SERDES_DATA4[31:0] O TX_SERDES_CLK[4] Data bus to SerDes4.
TX_SERDES_DATA5[31:0] O TX_SERDES_CLK[5] Data bus to SerDes5.
TX_SERDES_DATA6[31:0] O TX_SERDES_CLK[6] Data bus to SerDes6.
TX_SERDES_DATA7[31:0] O TX_SERDES_CLK[7] Data bus to SerDes7.
TX_SERDES_DATA8[31:0] O TX_SERDES_CLK[8] Data bus to SerDes8.
TX_SERDES_DATA9[31:0] O TX_SERDES_CLK[9] Data bus to SerDes9.
RX_SERDES_CLK[9:0] I   Recovered clock of each SerDes lane. The RX_SERDES_DATA bus for each lane is synchronized to the positive edge of the corresponding bit of this bus.
RX_SERDES_RESET[9:0] I RX_SERDES_CLK[9:0] Reset for each RX SerDes lane. The recovered clock for each SerDes lane has associated with it an active-High reset. This signal should be 1 whenever the associated recovered clock is not operating at the correct frequency. Generally this signal is derived from a PLL lock signal. This reset signal should be held in reset until the serial transceiver (GT) is finished its initialization and the RX_SERDES_CLK is stable.
Table 2. LBUS Interface – Clock/Reset Signals
Name I/O Domain Description
TX_CLK I   TX clock. All TX signals between the 100G Ethernet subsystem and the user-side logic are synchronized to the positive edge of this signal. The clock frequency is equal to the line rate divided by the SerDes width. This frequency is nominally 322.265625 MHz.
RX_CLK I   RX clock. All RX signals between the 100G Ethernet subsystem and the user-side logic are synchronized to the positive edge of this signal. The frequency of this clock should be the same as the TX clock.
RX_RESET I async (5 ns min) Reset for the RX circuits. This signal is active-High (1 = reset) and must be held High until RX_CLK is stable.The 100G Ethernet subsystem handles synchronizing the RX_RESET input to the appropriate clock domains within the 100G Ethernet subsystem.
TX_RESET I async (5 ns min) Reset for the TX circuits. This signal is active-High (1 = reset) and must be held High until TX_CLK is stable. The 100G Ethernet subsystem handles synchronizing the TX_RESET input to the appropriate clock domains within the 100G Ethernet subsystem.
Table 3. LBUS Interface – RX Path Signals
Name I/O Domain Description
RX_DATAOUT0[127:0] O RX_CLK Receive segmented LBUS Data for segment 0. The value of this bus is only valid in cycles that RX_ENAOUT0 is sampled as 1.
RX_DATAOUT1[127:0] O RX_CLK Receive segmented LBUS Data for segment1.
RX_DATAOUT2[127:0] O RX_CLK Receive segmented LBUS Data for segment2.
RX_DATAOUT3[127:0] O RX_CLK Receive segmented LBUS Data for segment3.
RX_ENAOUT0 O RX_CLK Receive LBUS Enable for segment0. This signal qualifies the other signals of the RX segmented LBUS Interface. Signals of the RX LBUS Interface are only valid in cycles in which RX_ENAOUT is sampled as a 1.
RX_ENAOUT1 O RX_CLK Receive LBUS Enable for segment1.
RX_ENAOUT2 O RX_CLK Receive LBUS Enable for segment2.
RX_ENAOUT3 O RX_CLK Receive LBUS Enable for segment3.
RX_SOPOUT0 O RX_CLK Receive LBUS start of packet (SOP) for segment0. This signal indicates the SOP when it is sampled as a 1 and is only valid in cycles in which RX_ENAOUT is sampled as a 1.
RX_SOPOUT1 O RX_CLK Receive LBUS SOP for segment1.
RX_SOPOUT2 O RX_CLK Receive LBUS SOP for segment2.
RX_SOPOUT3 O RX_CLK Receive LBUS SOP for segment3.
RX_EOPOUT0 O RX_CLK Receive LBUS end of packet (EOP) for segment0. This signal indicates the EOP when it is sampled as a 1 and is only valid in cycles in which RX_ENAOUT is sampled as a 1.
RX_EOPOUT1 O RX_CLK Receive LBUS EOP for segment1.
RX_EOPOUT2 O RX_CLK Receive LBUS EOP for segment2.
RX_EOPOUT3 O RX_CLK Receive LBUS EOP for segment3.
RX_ERROUT0 O RX_CLK Receive LBUS Error for segment0. This signal indicates that the current packet being received has an error when it is sampled as a 1. This signal is only valid in cycles when both RX_ENAOUT and RX_EOPOUT are sampled as a 1. When this signal is a value of 0, it indicates that there is no error in the packet being received.
RX_ERROUT1 O RX_CLK Receive LBUS Error for segment1.
RX_ERROUT2 O RX_CLK Receive LBUS Error for segment2.
RX_ERROUT3 O RX_CLK Receive LBUS Error for segment3.
RX_MTYOUT0[3:0] O RX_CLK Receive LBUS Empty for segment0. This bus indicates how many bytes of the RX_DATAOUT bus are empty or invalid for the last transfer of the current packet. This bus is only valid in cycles when both RX_ENAOUT and RX_EOPOUT are sampled as 1. When RX_ERROUT and RX_ENAOUT are sampled as 1, the value of RX_MTYOUT[2:0] is always 000. Other bits of RX_MTYOUT are as usual.
RX_MTYOUT1[3:0] O RX_CLK Receive LBUS Empty for segment1.
RX_MTYOUT2[3:0] O RX_CLK Receive LBUS Empty for segment2.
RX_MTYOUT3[3:0] O RX_CLK Receive LBUS Empty for segment3.
Table 4. LBUS Interface – TX Path Signals
Name I/O Domain Description
TX_RDYOUT O TX_CLK

Transmit LBUS Ready. This signal indicates whether the dedicated 100G Ethernet subsystem TX path is ready to accept data and provides back-pressure to the user logic. A value of 1 means the user logic can pass data to the 100G Ethernet subsystem. A value of 0 means the user logic must stop transferring data to the 100G Ethernet subsystem within four cycles or there will be an overflow.

If TX_RDYOUT goes to 0, it causes user logic to stop transferring data in the middle of a packet, and user logic must resume transferring data within 4 cycle of TX_RDYOUT returning to a value of 1.
TX_OVFOUT O TX_CLK Transmit LBUS Overflow. This signal indicates whether you have violated the back-pressure mechanism provided by the TX_RDYOUT signal. If TX_OVFOUT is sampled as a 1, a violation has occurred. It is up to you to design the rest of the user logic to not overflow the TX interface. In the event of an overflow condition, the TX path must be reset.
TX_UNFOUT O TX_CLK Transmit LBUS Underflow. This signal indicates whether you have under-run the LBUS interface. If TX_UNFOUT is sampled as 1, a violation has occurred meaning the current packet is corrupted. Error control blocks are transmitted as long as the underflow condition persists. It is up to the user logic to ensure a complete packet is input to the subsystem without under-running the LBUS interface.
TX_DATAIN0[127:0] I TX_CLK Transmit segmented LBUS Data for segment0. This bus receives input data from the user logic. The value of the bus is captured in every cycle that TX_ENAIN is sampled as 1.
TX_DATAIN1[127:0] I TX_CLK Transmit segmented LBUS Data for segment1.
TX_DATAIN2[127:0] I TX_CLK Transmit segmented LBUS Data for segment2.
TX_DATAIN3[127:0] I TX_CLK Transmit segmented LBUS Data for segment3.
TX_ENAIN0 I TX_CLK Transmit LBUS Enable for segment0. This signal is used to enable the TX LBUS Interface. All signals on this interface are sampled only in cycles in which TX_ENAIN is sampled as a 1.
TX_ENAIN1 I TX_CLK Transmit LBUS Enable for segment1.
TX_ENAIN2 I TX_CLK Transmit LBUS Enable for segment2.
TX_ENAIN3 I TX_CLK Transmit LBUS Enable for segment3.
TX_SOPIN0 I TX_CLK Transmit LBUS SOP for segment0. This signal is used to indicate the SOP when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles in which TX_ENAIN is sampled as a 1.
TX_SOPIN1 I TX_CLK Transmit LBUS SOP for segment1.
TX_SOPIN2 I TX_CLK Transmit LBUS SOP for segment2.
TX_SOPIN3 I TX_CLK Transmit LBUS SOP for segment3.
TX_EOPIN0 I TX_CLK Transmit LBUS EOP for segment0. This signal is used to indicate the EOP when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles in which TX_ENAIN is sampled as a 1.
TX_EOPIN1 I TX_CLK Transmit LBUS EOP for segment1.
TX_EOPIN2 I TX_CLK Transmit LBUS EOP for segment2.
TX_EOPIN3 I TX_CLK Transmit LBUS EOP for segment3.
TX_ERRIN0 I TX_CLK Transmit LBUS Error for segment0. This signal is used to indicate a packet contains an error when it is sampled as a 1 and is 0 for all other transfers of the packet. This signal is sampled only in cycles in which TX_ENAIN and TX_EOPIN are sampled as 1. When this signal is sampled as a 1, the last data word is replaced with the IEEE standard 802.3-2012 Error Code control word that guarantees the partner device receives the packet in error. If a packet is input with this signal set to a 1, the FCS checking and reporting is disabled (only for that packet).
TX_ERRIN1 I TX_CLK Transmit LBUS Error for segment1.
TX_ERRIN2 I TX_CLK Transmit LBUS Error for segment2.
TX_ERRIN3 I TX_CLK Transmit LBUS Error for segment3.
TX_MTYIN0[3:0] I TX_CLK Transmit LBUS Empty for segment0. This bus is used to indicate how many bytes of the TX_DATAIN bus are empty or invalid for the last transfer of the current packet. This bus is sampled only in cycles that TX_ENAIN and TX_EOPIN are sampled as 1. When TX_EOPIN and TX_ERRIN are sampled as 1, the value of TX_MTYIN[2:0] is ignored as treated as if it was 000. The other bits of TX_MTYIN are used as usual.
TX_MTYIN1[3:0] I TX_CLK Transmit LBUS Empty for segment1.
TX_MTYIN2[3:0] I TX_CLK Transmit LBUS Empty for segment2.
TX_MTYIN3[3:0] I TX_CLK Transmit LBUS Empty for segment3.
Table 5. LBUS Interface – TX Path Control/Status Signals
Name I/O Domain Description
CTL_TX_ENABLE I TX_CLK TX Enable. This signal is used to enable the transmission of data when it is sampled as a 1. When sampled as a 0, only idles are transmitted by the 100G Ethernet subsystem. This input should not be set to 1 until the receiver it is sending data to (that is, the receiver in the other device) is fully aligned and ready to receive data (that is, the other device is not sending a remote fault condition). Otherwise, loss of data can occur. If this signal is set to 0 while a packet is being transmitted, the current packet transmission is completed and then the 100G Ethernet subsystem stops transmitting anymore packets.
CTL_TX_SEND_LFI I TX_CLK Transmit Local Fault Indication (LFI) code word. If this input is sampled as a 1, the TX path only transmits Local Fault code words.
CTL_TX_SEND_RFI I TX_CLK Transmit Remote Fault Indication (RFI) code word. If this input is sampled as a 1, the TX path only transmits Remote Fault code words. This input should be set to 1 until the RX path is fully aligned and is ready to accept data from the link partner.
CTL_TX_SEND_IDLE I TX_CLK Transmit Idle code words. If this input is sampled as a 1, the TX path only transmits Idle code words. This input should be set to 1 when the partner device is sending Remote Fault Indication (RFI) code words.
TX_PREAMBLEIN[55:0] I TX_CLK Custom TX preamble input data. It should be valid during the start of packet.
STAT_TX_LOCAL_FAULT O TX_CLK A value of 1 indicates the transmit encoder state machine is in the TX_INIT state. This output is level sensitive.
Table 6. LBUS Interface – RX Path Control/Status Signals
Name I/O Domain Description
CTL_RX_ENABLE I RX_CLK RX Enable. For normal operation, this input must be set to 1. When this input is set the to 0, after the RX completes the reception of the current packet (if any), it stops receiving packets by keeping the PCS from decoding incoming data. In this mode, there are no statistics reported and the LBUS interface is idle.
CTL_RX_FORCE_RESYNC I

async

(5 ns min)

RX force resynchronization input. This signal is used to force the RX path to reset, re-synchronize, and realign. A value of 1 forces the reset operation. A value of 0 allows normal operation.

  • This input should normally be Low and should only be pulsed (one cycle minimum pulse) to force realignment.
RX_PREAMBLEOUT[55:0] O RX_CLK RX preamble output data.
STAT_RX_FRAMING_ERR_0[1:0] O RX_CLK RX sync header bits framing error for lane 0. Each PCS Lane has a two-bit bus that indicates how many sync header errors were received for that PCS Lane. The value of the bus is only valid when the corresponding STAT_RX_FRAMING_ERR_VALID_[19:0] is a 1. The values on these buses can be updated at any time and are intended to be used as increment values for sync header error counters.
STAT_RX_FRAMING_ERR_1[1:0] O RX_CLK RX sync header bits framing error for lane 1.
STAT_RX_FRAMING_ERR_2[1:0] O RX_CLK RX sync header bits framing error for lane 2.
STAT_RX_FRAMING_ERR_3[1:0] O RX_CLK RX sync header bits framing error for lane 3.
STAT_RX_FRAMING_ERR_4[1:0] O RX_CLK RX sync header bits framing error for lane 4.
STAT_RX_FRAMING_ERR_5[1:0] O RX_CLK RX sync header bits framing error for lane 5.
STAT_RX_FRAMING_ERR_6[1:0] O RX_CLK RX sync header bits framing error for lane 6.
STAT_RX_FRAMING_ERR_7[1:0] O RX_CLK RX sync header bits framing error for lane 7.
STAT_RX_FRAMING_ERR_8[1:0] O RX_CLK RX sync header bits framing error for lane 8.
STAT_RX_FRAMING_ERR_9[1:0] O RX_CLK RX sync header bits framing error for lane 9.
STAT_RX_FRAMING_ERR_10[1:0] O RX_CLK RX sync header bits framing error for lane 10.
STAT_RX_FRAMING_ERR_11[1:0] O RX_CLK RX sync header bits framing error for lane 11.
STAT_RX_FRAMING_ERR_12[1:0] O RX_CLK RX sync header bits framing error for lane 12.
STAT_RX_FRAMING_ERR_13[1:0] O RX_CLK RX sync header bits framing error for lane 13.
STAT_RX_FRAMING_ERR_14[1:0] O RX_CLK RX sync header bits framing error for lane 14.
STAT_RX_FRAMING_ERR_15[1:0] O RX_CLK RX sync header bits framing error for lane 15.
STAT_RX_FRAMING_ERR_16[1:0] O RX_CLK RX sync header bits framing error for lane 16.
STAT_RX_FRAMING_ERR_17[1:0] O RX_CLK RX sync header bits framing error for lane 17.
STAT_RX_FRAMING_ERR_18[1:0] O RX_CLK RX sync header bits framing error for lane 18.
STAT_RX_FRAMING_ERR_19[1:0] O RX_CLK RX sync header bits framing error for lane 19.
STAT_RX_FRAMING_ERR_VALID_0 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_0[1:0]. When this output is sampled as a 1, the value on the corresponding STAT_RX_FRAMING_ERR_0[1:0] is valid.
STAT_RX_FRAMING_ERR_VALID_1 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_1[1:0].
STAT_RX_FRAMING_ERR_VALID_2 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_2[1:0].
STAT_RX_FRAMING_ERR_VALID_3 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_3[1:0].
STAT_RX_FRAMING_ERR_VALID_4 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_4[1:0].
STAT_RX_FRAMING_ERR_VALID_5 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_5[1:0].
STAT_RX_FRAMING_ERR_VALID_6 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_6[1:0].
STAT_RX_FRAMING_ERR_VALID_7 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_7[1:0].
STAT_RX_FRAMING_ERR_VALID_8 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_8[1:0].
STAT_RX_FRAMING_ERR_VALID_9 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_9[1:0].
STAT_RX_FRAMING_ERR_VALID_10 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_10[1:0].
STAT_RX_FRAMING_ERR_VALID_11 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_11[1:0].
STAT_RX_FRAMING_ERR_VALID_12 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_12[1:0].
STAT_RX_FRAMING_ERR_VALID_13 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_13[1:0].
STAT_RX_FRAMING_ERR_VALID_14 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_14[1:0].
STAT_RX_FRAMING_ERR_VALID_15 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_15[1:0].
STAT_RX_FRAMING_ERR_VALID_16 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_16[1:0].
STAT_RX_FRAMING_ERR_VALID_17 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_17[1:0].
STAT_RX_FRAMING_ERR_VALID_18 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_18[1:0].
STAT_RX_FRAMING_ERR_VALID_19 O RX_CLK Valid indicator for STAT_RX_FRAMING_ERR_19[1:0].
STAT_RX_LOCAL_FAULT O RX_CLK This output is High when STAT_RX_INTERNAL_LOCAL_FAULT or STAT_RX_RECEIVED_LOCAL_FAULT is asserted. This output is level sensitive.
STAT_RX_SYNCED[19:0] O RX_CLK Word Boundary Synchronized. These signals indicate whether a PCS lane is word-boundary synchronized. A value of 1 indicates the corresponding PCS lane has achieved word-boundary synchronization and it has received a PCS lane marker. Corresponds to MDIO register bit 3.52.7:0 and 3.53.11:0 as defined in Clause 82.3. This output is level sensitive.
STAT_RX_SYNCED_ERR[19:0] O RX_CLK Word Boundary Synchronization Error. These signals indicate whether an error occurred during word boundary synchronization in the respective PCS lane. A value of 1 indicates that the corresponding PCS lane lost word boundary synchronization due to sync header framing bits errors or that a PCS lane marker was never received. This output is level sensitive.
STAT_RX_MF_LEN_ERR[19:0] O RX_CLK PCS Lane Marker Length Error. These signals indicate whether a PCS Lane Marker length mismatch occurred in the respective lane (that is, PCS Lane Markers were received not every CTL_RX_VL_LENGTH_MINUS1 + 1 words apart). A value of 1 indicates that the corresponding lane is receiving PCS Lane Markers at wrong intervals. This output remains High until the error condition is removed.
STAT_RX_MF_REPEAT_ERR[19:0] O RX_CLK PCS Lane Marker Consecutive Error. These signals indicate whether four consecutive PCS Lane Marker errors occurred in the respective lane. A value of 1 indicates an error in the corresponding lane. This output remains High until the error condition is removed.
STAT_RX_MF_ERR[19:0] O RX_CLK PCS Lane Marker Word Error. These signals indicate that an incorrectly formed PCS Lane Marker Word was detected in the respective lane. A value of 1 indicates an error occurred. This output is pulsed for one clock cycle to indicate the error condition. Pulses can occur in back-to-back cycles.
STAT_RX_ALIGNED O RX_CLK All PCS Lanes Aligned/De-Skewed. This signal indicates whether or not all PCS lanes are aligned and de-skewed. A value of 1 indicates all PCS lanes are aligned and de-skewed. When this signal is a 1, the RX path is aligned and can receive packet data. When this signal is 0, a local fault condition exists. Also corresponds to MDIO register bit 3.50.12 as defined in Clause 82.3. This output is level sensitive.
STAT_RX_STATUS O RX_CLK PCS status. A value of 1 indicates that the PCS is aligned and not in HI_BER state. Corresponds to Management Data Input/Output (MDIO) register bit 3.32.12 as defined in Clause 82.3. This output is level sensitive.
STAT_RX_BLOCK_LOCK[19:0] O RX_CLK Block lock status for each PCS lane. A value of 1 indicates that the corresponding lane has achieved block lock as defined in Clause 82. Corresponds to MDIO register bit 3.50.7:0 and 3.51.11:0 as defined in Clause 82.3. This output is level sensitive.
STAT_RX_ALIGNED_ERR O RX_CLK Loss of Lane Alignment/De-Skew. This signal indicates that an error occurred during PCS lane alignment or PCS lane alignment was lost. A value of 1 indicates an error occurred. This output is level sensitive.
STAT_RX_MISALIGNED O RX_CLK

Alignment Error. This signal indicates that the lane aligner did not receive the expected PCS lane marker across all lanes. This signal is not asserted until the PCS lane marker has been received at least once across all lanes and at least one incorrect lane marker has been received. This occurs one metaframe after the error.

This signal is not asserted if the lane markers have never been received correctly. Lane marker errors are indicated by the corresponding STAT_RX_MF_ERR signal.

This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.
STAT_RX_REMOTE_FAULT O RX_CLK Remote fault indication status. If this bit is sampled as a 1, it indicates a remote fault condition was detected. If this bit is sampled as a 0, a remote fault condition exist does not exist. This output is level sensitive.
STAT_RX_PCSL_NUMBER_0[4:0] O RX_CLK The signal stat_rx_pcsl_number_0[4:0] indicates which PCS lane is received on physical lane 0. There are a total of 20 separate STAT_RX_PCSL_NUMBER[4:0] buses This bus is only valid when the corresponding bit of STAT_RX_SYNCED[19:0] is a 1. These outputs are level sensitive.
STAT_RX_PCSL_NUMBER_1[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 1.
STAT_RX_PCSL_NUMBER_2[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 2.
STAT_RX_PCSL_NUMBER_3[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 3.
STAT_RX_PCSL_NUMBER_4[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 4.
STAT_RX_PCSL_NUMBER_5[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 5.
STAT_RX_PCSL_NUMBER_6[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 6.
STAT_RX_PCSL_NUMBER_7[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 7.
STAT_RX_PCSL_NUMBER_8[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 8.
STAT_RX_PCSL_NUMBER_9[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 9.
STAT_RX_PCSL_NUMBER_10[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 10.
STAT_RX_PCSL_NUMBER_11[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 11.
STAT_RX_PCSL_NUMBER_12[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 12.
STAT_RX_PCSL_NUMBER_13[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 13.
STAT_RX_PCSL_NUMBER_14[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 14.
STAT_RX_PCSL_NUMBER_15[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 15.
STAT_RX_PCSL_NUMBER_16[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 16.
STAT_RX_PCSL_NUMBER_17[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 17.
STAT_RX_PCSL_NUMBER_18[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 18.
STAT_RX_PCSL_NUMBER_19[4:0] O RX_CLK This signal indicates which PCS lane is received on physical lane 19.
STAT_RX_PCSL_DEMUXED[19:0] O RX_CLK PCS Lane Marker found. If a signal of this bus is sampled as 1, it indicates that the receiver has properly de-multiplexed that PCS lane. These outputs are level sensitive.
STAT_RX_BAD_FCS[2:0] O RX_CLK Bad FCS indicator. A value of 1 indicates a packet was received with a bad FCS, but not a stomped FCS. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.
STAT_RX_STOMPED_FCS[2:0] O RX_CLK Stomped FCS indicator. A value of 1 or greater indicates that one or more packets were received with a stomped FCS. A stomped FCS is defined as the bitwise inverse of the expected good FCS. This output is pulsed for one clock cycle to indicate the stomped condition. Pulses can occur in back-to-back cycles.
STAT_RX_TRUNCATED O RX_CLK Packet truncation indicator. A value of 1 indicates that the current packet in flight is truncated due to its length exceeding CTL_RX_MAX_PACKET_LEN[14:0]. This output is pulsed for one clock cycle to indicate the truncated condition. Pulses can occur in back-to-back cycles.
STAT_RX_INTERNAL_LOCAL_FAULT O RX_CLK This signal goes High when an internal local fault is generated due to any one of the following: test pattern generation, bad lane alignment, or high bit error rate. This signal remains High as long as the fault condition persists.
STAT_RX_RECEIVED_LOCAL_FAULT O RX_CLK This signal goes High when enough local fault words are received from the link partner to trigger a fault condition as specified by the IEEE fault state machine. This signal remains High as long as the fault condition persists.
STAT_RX_BIP_ERR_0 O RX_CLK BIP8 error indicator for PCS lane 0. A non-zero value indicates the BIP8 signature byte was in error for the corresponding PCS lane. A non-zero value is pulsed for one clock cycle. This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.
STAT_RX_BIP_ERR_1 O RX_CLK BIP8 error indicator for PCS lane 1.
STAT_RX_BIP_ERR_2 O RX_CLK BIP8 error indicator for PCS lane 2.
STAT_RX_BIP_ERR_3 O RX_CLK BIP8 error indicator for PCS lane 3.
STAT_RX_BIP_ERR_4 O RX_CLK BIP8 error indicator for PCS lane 4.
STAT_RX_BIP_ERR_5 O RX_CLK BIP8 error indicator for PCS lane 5.
STAT_RX_BIP_ERR_6 O RX_CLK BIP8 error indicator for PCS lane 6.
STAT_RX_BIP_ERR_7 O RX_CLK BIP8 error indicator for PCS lane 7.
STAT_RX_BIP_ERR_8 O RX_CLK BIP8 error indicator for PCS lane 8.
STAT_RX_BIP_ERR_9 O RX_CLK BIP8 error indicator for PCS lane 9.
STAT_RX_BIP_ERR_10 O RX_CLK BIP8 error indicator for PCS lane 10.
STAT_RX_BIP_ERR_11 O RX_CLK BIP8 error indicator for PCS lane 11.
STAT_RX_BIP_ERR_12 O RX_CLK BIP8 error indicator for PCS lane 12.
STAT_RX_BIP_ERR_13 O RX_CLK BIP8 error indicator for PCS lane 13.
STAT_RX_BIP_ERR_14 O RX_CLK BIP8 error indicator for PCS lane 14.
STAT_RX_BIP_ERR_15 O RX_CLK BIP8 error indicator for PCS lane 15.
STAT_RX_BIP_ERR_16 O RX_CLK BIP8 error indicator for PCS lane 16.
STAT_RX_BIP_ERR_17 O RX_CLK BIP8 error indicator for PCS lane 17.
STAT_RX_BIP_ERR_18 O RX_CLK BIP8 error indicator for PCS lane 18.
STAT_RX_BIP_ERR_19 O RX_CLK BIP8 error indicator for PCS lane 19.
STAT_RX_HI_BER O RX_CLK High Bit Error Rate (BER) indicator. When set to 1, the BER is too high as defined by the 802.3. Corresponds to MDIO register bit 3.32.1 as defined in Clause 82.3. This output is level sensitive.
Table 7. Miscellaneous Status/Control Signals
Name I/O Domain Description
STAT_RX_GOT_SIGNAL_OS O RX_CLK Signal Ordered Sets (OS) indication. If this bit is sampled as a 1, it indicates that a Signal OS word was received. Signal OS should not be received in an Ethernet network.
CTL_RX_TEST_PATTERN I RX_CLK Test pattern checking enable for the RX core. A value of 1 enables test mode as defined in Clause 82.2.18. Corresponds to MDIO register bit 3.42.2 as defined in Clause 82.3. Checks for scrambled idle pattern.
CTL_TX_TEST_PATTERN I TX_CLK Test pattern generation enable for the TX core. A value of 1 enables test mode as defined in Clause 82.2.18. Corresponds to MDIO register bit 3.42.3 as defined in Clause 82.3. Generates a scrambled idle pattern.

STAT_RX_TEST_PATTERN_

MISMATCH[2:0]

 O RX_CLK Test pattern mismatch increment. A non-zero value in any cycle indicates how many mismatches occurred for the test pattern in the RX core. This output is only active when CTL_RX_TEST_PATTERN is set to a 1. This output can be used to generate MDIO register 3.43.15:0 as defined in Clause 82.3. This output is pulsed for one clock cycle.
CTL_CAUI4_MODE I async state When this input is High, the dedicated 100G Ethernet subsystem operates in CAUI-4 mode and when Low in CAUI-10 mode.
CTL_TX_LANE0_VLM_BIP7_OVERRIDE I TX_CLK When this input is High, the bip7 byte of the PCS lane0 marker is over-ridden by CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[7:0]
CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE[7:0] I TX_CLK This input is the override value of the bip7 byte of PCS lane0 marker when CTL_TX_LANE0_VLM_BIP7_OVERRIDE is asserted.
STAT_RX_LANE0_VLM_BIP7[7:0] O RX_CLK This output is the received value of the bip7 byte in the PCS lane0 marker.
STAT_RX_LANE0_VLM_BIP7_VALID O RX_CLK This output, when asserted, indicates that the value of STAT_RX_LANE0_VLM_BIP[7:0] is valid.
Table 8. Statistics Interface – RX Path
Name I/O Domain Description
STAT_RX_TOTAL_BYTES[6:0] O RX_CLK Increment for the total number of bytes received.
STAT_RX_TOTAL_PACKETS[2:0] O RX_CLK Increment for the total number of packets received.
STAT_RX_TOTAL_GOOD_BYTES[13:0] O RX_CLK Increment for the total number of good bytes received. This value is only non-zero when a packet is received completely and contains no errors.
STAT_RX_TOTAL_GOOD_PACKETS O RX_CLK Increment for the total number of good packets received. This value is only non-zero when a packet is received completely and contains no errors.
STAT_RX_PACKET_BAD_FCS O RX_CLK Increment for packets between 64 and ctl_rx_max_packet_len bytes that have FCS errors.
STAT_RX_PACKET_64_BYTES O RX_CLK Increment for good and bad packets received that contain 64 bytes.
STAT_RX_PACKET_65_127_BYTES O RX_CLK Increment for good and bad packets received that contain 65 to 127 bytes.
STAT_RX_PACKET_128_255_BYTES O RX_CLK Increment for good and bad packets received that contain 128 to 255 bytes.
STAT_RX_PACKET_256_511_BYTES O RX_CLK Increment for good and bad packets received that contain 256 to 511 bytes.
STAT_RX_PACKET_512_1023_BYTES O RX_CLK Increment for good and bad packets received that contain 512 to 1,023 bytes.
STAT_RX_PACKET_1024_1518_BYTES O RX_CLK Increment for good and bad packets received that contain 1,024 to 1,518 bytes.
STAT_RX_PACKET_1519_1522_BYTES O RX_CLK Increment for good and bad packets received that contain 1,519 to 1,522 bytes.
STAT_RX_PACKET_1523_1548_BYTES O RX_CLK Increment for good and bad packets received that contain 1,523 to 1,548 bytes.
STAT_RX_PACKET_1549_2047_BYTES O RX_CLK Increment for good and bad packets received that contain 1,549 to 2,047 bytes.
STAT_RX_PACKET_2048_4095_BYTES O RX_CLK Increment for good and bad packets received that contain 2,048 to 4,095 bytes.
STAT_RX_PACKET_4096_8191_BYTES O RX_CLK Increment for good and bad packets received that contain 4,096 to 8,191 bytes.
STAT_RX_PACKET_8192_9215_BYTES O RX_CLK Increment for good and bad packets received that contain 8,192 to 9,215 bytes.
STAT_RX_PACKET_SMALL[2:0] O RX_CLK Increment for all packets that are less than 64 bytes long.
STAT_RX_PACKET_LARGE O RX_CLK Increment for all packets that are more than 9215 bytes long.
STAT_RX_UNICAST O RX_CLK Increment for good unicast packets.
STAT_RX_MULTICAST O RX_CLK Increment for good multicast packets.
STAT_RX_BROADCAST O RX_CLK Increment for good broadcast packets.
STAT_RX_OVERSIZE O RX_CLK Increment for packets longer than CTL_RX_MAX_PACKET_LEN with good FCS.
STAT_RX_TOOLONG O RX_CLK Increment for packets longer than CTL_RX_MAX_PACKET_LEN with good and bad FCS.
STAT_RX_UNDERSIZE[2:0] O RX_CLK Increment for packets shorter than STAT_RX_MIN_PACKET_LEN with good FCS.
STAT_RX_FRAGMENT[2:0] O RX_CLK Increment for packets shorter than stat_rx_min_packet_len with bad FCS.
STAT_RX_VLAN O RX_CLK Increment for good 802.1Q tagged VLAN packets.
STAT_RX_INRANGEERR O RX_CLK Increment for packets with Length field error but with good FCS.
STAT_RX_JABBER O RX_CLK Increment for packets longer than CTL_RX_MAX_PACKET_LEN with bad FCS.
STAT_RX_PAUSE O RX_CLK Increment for 802.3x Ethernet MAC Pause packet with good FCS.
STAT_RX_USER_PAUSE O RX_CLK Increment for priority based pause packets with good FCS.
STAT_RX_BAD_CODE[2:0] O RX_CLK Increment for 64B/66B code violations. This signal indicates that the RX PCS receive state machine is in the RX_E state as specified by the 802.3 specifications. This output can be used to generate MDIO register 3.33:7:0 as defined in Clause 82.3.
STAT_RX_BAD_SFD O RX_CLK Increment bad SFD. This signal indicates if the Ethernet packet received was preceded by a valid SFD. A value of 1 indicates that an invalid SFD was received.
STAT_RX_BAD_PREAMBLE O RX_CLK Increment bad preamble. This signal indicates if the Ethernet packet received was preceded by a valid preamble. A value of 1 indicates that an invalid preamble was received.
Table 9. Statistics Interface – TX Path
Name I/O Domain Description
STAT_TX_TOTAL_BYTES[5:0] O TX_CLK Increment for the total number of bytes transmitted.
STAT_TX_TOTAL_PACKETS O TX_CLK Increment for the total number of packets transmitted.
STAT_TX_TOTAL_GOOD_BYTES[13:0] O TX_CLK Increment for the total number of good bytes transmitted. This value is only non-zero when a packet is transmitted completely and contains no errors.
STAT_TX_TOTAL_GOOD_PACKETS O TX_CLK Increment for the total number of good packets transmitted.
STAT_TX_BAD_FCS O TX_CLK Increment for packets greater than 64 bytes that have FCS errors.
STAT_TX_PACKET_64_BYTES O TX_CLK Increment for good and bad packets transmitted that contain 64 bytes.
STAT_TX_PACKET_65_127_BYTES O TX_CLK Increment for good and bad packets transmitted that contain 65 to 127 bytes.
STAT_TX_PACKET_128_255_BYTES O TX_CLK Increment for good and bad packets transmitted that contain 128 to 255 bytes.
STAT_TX_PACKET_256_511_BYTES O TX_CLK Increment for good and bad packets transmitted that contain 256 to 511 bytes.
STAT_TX_PACKET_512_1023_BYTES O TX_CLK Increment for good and bad packets transmitted that contain 512 to 1,023 bytes.
STAT_TX_PACKET_1024_1518_BYTES O TX_CLK Increment for good and bad packets transmitted that contain 1,024 to 1,518 bytes.
STAT_TX_PACKET_1519_1522_BYTES O TX_CLK Increment for good and bad packets transmitted that contain 1,519 to 1,522 bytes.
STAT_TX_PACKET_1523_1548_BYTES O TX_CLK Increment for good and bad packets transmitted that contain 1,523 to 1,548 bytes.
STAT_TX_PACKET_1549_2047_BYTES O TX_CLK Increment for good and bad packets transmitted that contain 1,549 to 2,047 bytes.
STAT_TX_PACKET_2048_4095_BYTES O TX_CLK Increment for good and bad packets transmitted that contain 2,048 to 4,095 bytes.
STAT_TX_PACKET_4096_8191_BYTES O TX_CLK Increment for good and bad packets transmitted that contain 4,096 to 8,191 bytes.
STAT_TX_PACKET_8192_9215_BYTES O TX_CLK Increment for good and bad packets transmitted that contain 8,192 to 9,215 bytes.
STAT_TX_PACKET_SMALL O TX_CLK Increment for all packets that are less than 64 bytes long. Packet transfers of less than 64 bytes are not permitted.
STAT_TX_PACKET_LARGE O TX_CLK Increment for all packets that are more than 9,215 bytes long.
STAT_TX_UNICAST O TX_CLK Increment for good unicast packets.
STAT_TX_MULTICAST O TX_CLK Increment for good multicast packets.
STAT_TX_BROADCAST O TX_CLK Increment for good broadcast packets.
STAT_TX_VLAN O TX_CLK Increment for good 802.1Q tagged VLAN packets.
STAT_TX_PAUSE O TX_CLK Increment for 802.3x Ethernet MAC Pause packet with good FCS.
STAT_TX_USER_PAUSE O TX_CLK Increment for priority based pause packets with good FCS.
STAT_TX_FRAME_ERROR O TX_CLK Increment for packets with tx_errin set to indicate an EOP abort.
Table 10. Pause Interface – Control Signals
Name I/O Domain Description
CTL_RX_PAUSE_ENABLE[8:0] I RX_CLK

RX pause enable signal. This input is used to enable the processing of the pause quanta for the corresponding priority.

This signal only affects the RX user interface, not the pause processing logic.
CTL_TX_PAUSE_ENABLE[8:0] I TX_CLK TX pause enable signal. This input is used to enable the processing of the pause quanta for the corresponding priority. This signal gates transmission of pause packets.
Table 11. Pause Interface – RX Path
Name I/O Domain Description
CTL_RX_ENABLE_GCP I RX_CLK A value of 1 enables global control packet processing.
CTL_RX_CHECK_MCAST_GCP I RX_CLK A value of 1 enables global control multicast destination address processing.
CTL_RX_CHECK_UCAST_GCP I RX_CLK A value of 1 enables global control unicast destination address processing.
CTL_RX_CHECK_SA_GCP I RX_CLK A value of 1 enables global control source address processing.
CTL_RX_CHECK_ETYPE_GCP I RX_CLK A value of 1 enables global control Ethertype processing.
CTL_RX_CHECK_OPCODE_GCP I RX_CLK A value of 1 enables global control opcode processing.
CTL_RX_ENABLE_PCP I RX_CLK A value of 1 enables priority control packet processing.
CTL_RX_CHECK_MCAST_PCP I RX_CLK A value of 1 enables priority control multicast destination address processing.
CTL_RX_CHECK_UCAST_PCP I RX_CLK A value of 1 enables priority control unicast destination address processing.
CTL_RX_CHECK_SA_PCP I RX_CLK A value of 1 enables priority control source address processing.
CTL_RX_CHECK_ETYPE_PCP I RX_CLK A value of 1 enables priority control Ethertype processing.
CTL_RX_CHECK_OPCODE_PCP I RX_CLK A value of 1 enables priority control opcode processing.
CTL_RX_ENABLE_GPP I RX_CLK A value of 1 enables global pause packet processing.
CTL_RX_CHECK_MCAST_GPP I RX_CLK A value of 1 enables global pause multicast destination address processing.
CTL_RX_CHECK_UCAST_GPP I RX_CLK A value of 1 enables global pause unicast destination address processing.
CTL_RX_CHECK_SA_GPP I RX_CLK A value of 1 enables global pause source address processing.
CTL_RX_CHECK_ETYPE_GPP I RX_CLK A value of 1 enables global pause Ethertype processing.
CTL_RX_CHECK_OPCODE_GPP I RX_CLK A value of 1 enables global pause opcode processing.
CTL_RX_ENABLE_PPP I RX_CLK A value of 1 enables priority pause packet processing.
CTL_RX_CHECK_MCAST_PPP I RX_CLK A value of 1 enables priority pause multicast destination address processing.
CTL_RX_CHECK_UCAST_PPP I RX_CLK A value of 1 enables priority pause unicast destination address processing.
CTL_RX_CHECK_SA_PPP I RX_CLK A value of 1 enables priority pause source address processing.
CTL_RX_CHECK_ETYPE_PPP I RX_CLK A value of 1 enables priority pause Ethertype processing.
CTL_RX_CHECK_OPCODE_PPP I RX_CLK A value of 1 enables priority pause opcode processing.
STAT_RX_PAUSE_REQ[8:0] O RX_CLK Pause request signal. When the RX receives a valid pause frame, it sets the corresponding bit of this bus to a 1 and holds at 1 until the pause packet has been processed. See Pause Processing Interface.
CTL_RX_PAUSE_ACK[8:0] I RX_CLK Pause acknowledge signal. This bus is used to acknowledge the receipt of the pause frame from the user logic. See Pause Processing Interface.
STAT_RX_PAUSE_VALID[8:0] O RX_CLK This bus indicates that a pause packet was received and the associated quanta on the STAT_RX_PAUSE_QUANTA[8:0][15:0] bus is valid and must be used for pause processing. If an 802.3x Ethernet MAC Pause packet is received, bit[8] is set to 1.
STAT_RX_PAUSE_QUANTA0[15:0] O RX_CLK This bus indicates the quanta received for priority 0 in priority based pause operation. If an 802.3x Ethernet MAC Pause packet is received, the quanta is placed in STAT_RX_PAUSE_QUANTA8[15:0].
STAT_RX_PAUSE_QUANTA1[15:0] O RX_CLK This bus indicates the quanta received for priority 1 in a priority based pause operation.
STAT_RX_PAUSE_QUANTA2[15:0] O RX_CLK This bus indicates the quanta received for priority 2 in a priority based pause operation.
STAT_RX_PAUSE_QUANTA3[15:0] O RX_CLK This bus indicates the quanta received for priority 3 in a priority based pause operation.
STAT_RX_PAUSE_QUANTA4[15:0] O RX_CLK This bus indicates the quanta received for priority 4 in a priority based pause operation.
STAT_RX_PAUSE_QUANTA5[15:0] O RX_CLK This bus indicates the quanta received for priority 5 in a priority based pause operation.
STAT_RX_PAUSE_QUANTA6[15:0] O RX_CLK This bus indicates the quanta received for priority 6 in a priority based pause operation.
STAT_RX_PAUSE_QUANTA7[15:0] O RX_CLK This bus indicates the quanta received for priority 7 in a priority based pause operation.
STAT_RX_PAUSE_QUANTA8[15:0] O RX_CLK This bus indicates the value of an 802.3x Ethernet MAC Pause packet when received.
Table 12. Pause Interface – TX Path
Name I/O Domain Description
CTL_TX_PAUSE_REQ[8:0] I TX_CLK If a bit of this bus is set to 1, the dedicated 100G Ethernet subsystem transmits a pause packet using the associated quanta value on the CTL_TX_PAUSE_QUANTA[8:0][15:0] bus. If bit[8] is set to 1, a global pause packet is transmitted. All other bits cause a priority pause packet to be transmitted. Each bit of this bus must be held at a steady state for a minimum of 16 cycles before the next transition.
CTL_TX_PAUSE_QUANTA0[15:0] I TX_CLK This bus indicates the quanta to be transmitted for priority 0 in a priority based pause operation. If an 802.3x Ethernet MAC Pause packet is to be transmitted, the quanta is placed in CTL_TX_PAUSE_QUANTA8[15:0].
CTL_TX_PAUSE_QUANTA1[15:0] I TX_CLK This bus indicates the quanta to be transmitted for priority 1 in a priority based pause operation.
CTL_TX_PAUSE_QUANTA2[15:0] I TX_CLK This bus indicates the quanta to be transmitted for priority 2 in a priority based pause operation.
CTL_TX_PAUSE_QUANTA3[15:0] I TX_CLK This bus indicates the quanta to be transmitted for priority 3 in a priority based pause operation.
CTL_TX_PAUSE_QUANTA4[15:0] I TX_CLK This bus indicates the quanta to be transmitted for priority 4 in a priority based pause operation.
CTL_TX_PAUSE_QUANTA5[15:0] I TX_CLK This bus indicates the quanta to be transmitted for priority 5 in a priority based pause operation.
CTL_TX_PAUSE_QUANTA6[15:0] I TX_CLK This bus indicates the quanta to be transmitted for priority 6 in a priority based pause operation.
CTL_TX_PAUSE_QUANTA7[15:0] I TX_CLK This bus indicates the quanta to be transmitted for priority 7 in a priority based pause operation.
CTL_TX_PAUSE_QUANTA8[15:0] I TX_CLK This bus indicates the value of an 802.3x MAC Pause packet to be transmitted.
CTL_TX_PAUSE_REFRESH_TIMER0[15:0] I TX_CLK This bus sets the retransmission time of pause packets for priority 0 in a priority based pause operation.
CTL_TX_PAUSE_REFRESH_TIMER1[15:0] I TX_CLK This bus sets the retransmission time of pause packets for priority 1 in a priority based pause operation.
CTL_TX_PAUSE_REFRESH_TIMER2[15:0] I TX_CLK This bus sets the retransmission time of pause packets for priority 2 in a priority based pause operation.
CTL_TX_PAUSE_REFRESH_TIMER3[15:0] I TX_CLK This bus sets the retransmission time of pause packets for priority 3 in a priority based pause operation.
CTL_TX_PAUSE_REFRESH_TIMER4[15:0] I TX_CLK This bus sets the retransmission time of pause packets for priority 4 in a priority based pause operation.
CTL_TX_PAUSE_REFRESH_TIMER5[15:0] I TX_CLK This bus sets the retransmission time of pause packets for priority 5 in a priority based pause operation.
CTL_TX_PAUSE_REFRESH_TIMER6[15:0] I TX_CLK This bus sets the retransmission time of pause packets for priority 6 in a priority based pause operation.
CTL_TX_PAUSE_REFRESH_TIMER7[15:0] I TX_CLK This bus sets the retransmission time of pause packets for priority 7 in a priority based pause operation.
CTL_TX_PAUSE_REFRESH_TIMER8[15:0] I TX_CLK This bus sets the retransmission time of pause packets for a global pause operation.
CTL_TX_RESEND_PAUSE I TX_CLK Re-transmit pending pause packets. When this input is sampled as 1, all pending pause packets are retransmitted as soon as possible (that is, after the current packet in flight is completed) and the retransmit counters are reset. This input should be pulsed to 1 for one cycle at a time.
STAT_TX_PAUSE_VALID[8:0] O TX_CLK If a bit of this bus is set to 1, the dedicated 100G Ethernet subsystem has transmitted a pause packet. If bit[8] is set to 1, a global pause packet is transmitted. All other bits cause a priority pause packet to be transmitted.
Table 13. IEEE 1588 Interface – TX Path
Name I/O Domain Description
CTL_TX_SYSTEMTIMERIN[80-1:0] I TX_CLK

System timer input for the TX.

In normal clock mode, the time format is according to the IEEE 1588 format, with 48 bits for seconds and 32 bits for nanoseconds.

In transparent clock mode, bit 63 is the sign bit, bits 62:16 carry nanoseconds, and bits 15:0 carry fractional nanoseconds. Refer to IEEE 1588v2 for the representational definitions.

This input must be in the TX clock domain.
TX_PTP_TSTAMP_VALID_OUT O TX_CLK This bit indicates that a valid timestamp is being presented on the TX.
TX_PTP_PCSLANE_OUT[5-1:0] O TX_CLK This bus identifies which of the 20 PCS lanes that the SOP was detected on for the corresponding timestamp.
TX_PTP_TSTAMP_TAG_OUT[15:0] O TX_CLK Tag output corresponding to TX_PTP_TAG_FIELD_IN[15:0].
TX_PTP_TSTAMP_OUT[79:0] O TX_CLK

Time stamp for the transmitted packet SOP corresponding to the time at which it passed the capture plane.

The representation of the bits contained in this bus is the same as the timer input.
TX_PTP_1588OP_IN[1:0] I TX_CLK
  • 2’b00 – “No operation”: no timestamp will be taken and the frame will not be modified.
  • 2’b01 – “1-step”: a timestamp should be taken and inserted into the frame.
  • 2’b10 – “2-step”: a timestamp should be taken and returned to the client using the additional ports of 2-step operation. The frame itself will not be modified.
  • 2’b11 – Reserved.
  • The CMAC subsystem samples this signal at SOP.
TX_PTP_TAG_FIELD_IN[15:0] I TX_CLK

The usage of this field is dependent on the 1588 operation

  • For “No operation”, this field will be ignored.
  • For “1-step” and “2-step”, this field is a tag field. This tag value will be returned to the client with the timestamp for the current frame using the additional ports of 2-step operation. This tag value can be used by software to ensure that the timestamp can be matched with the precise timing protocol (PTP) frame that it sent for transmission.
  • The CMAC subsystem samples this signal at SOP.
TX_PTP_UPD_CHKSUM_IN I TX_CLK

The usage of this field is dependent on the 1588 operation

  • For “No operation” or “2-step”, this bit will be ignored.
TX_PTP_CHKSUM_OFFSET_IN[15:0] I TX_CLK

The usage of this field is dependent on the “1588 operation” and on the “Update Checksum” bit.

  • For “No operation”, for “2-step” or for “1-step” when “Update Checksum” is set to 1’b0, this field will be ignored.
  • Only even values are supported.
  • The IPv6 header size is unbounded, so this field is able to cope with all frames sizes up to 16K jumbo frames. Only even values are supported.
TX_PTP_TSTAMP_OFFSET_IN[15:0] I TX_CLK

The usage of this field is dependent on the 1588 operation

  • For “No operation” or “2-step” this field will be ignored.

This input is also used to specify the offset for the correction field in 1-step Transparent Clock mode.

  • The IPv6 header size is unbounded, so this field is able to cope with all frames sizes up to 16K jumbo frames.
  • Only even values are supported.
  • In transparent clock mode and when tx_ptp_upd_chksum_in=1, this value cannot be greater than tx_ptp_chksum_offset_in + 34 (decimal).
CTL_TX_PTP_VLANE_ADJUST_MODE I async state

When asserted, this signal applies an adjustment to the TX timestamps according to the PCS lane on which the SOP occurs. When zero, no adjustment is made.

This signal only has effect for 1-step operation.
TX_PTP_RXTSTAMP_IN[63:0] I TX_CLK Reserved
STAT_TX_PTP_FIFO_WRITE_ERROR O TX_CLK Transmit PTP FIFO write error. A 1 on this status indicates that an error occurred during the PTP Tag write. A TX Path reset is required to clear the error.
STAT_TX_PTP_FIFO_READ_ERROR O TX_CLK Transmit PTP FIFO read error. A 1 on this status indicates that an error occurred during the PTP Tag read. A TX Path reset is required to clear the error.
Table 14. IEEE 1588 Interface – RX Path
Name I/O Domain Description
CTL_RX_SYSTEMTIMERIN[80-1:0] I RX_SERDES_CLK[0]

System timer input for the RX.

In normal clock mode, the time format is according to the IEEE 1588 format, with 48 bits for seconds and 32 bits for nanoseconds.

In transparent clock mode, bit 63 is the sign bit, bits 62:16 carry nanoseconds, and bits 15:0 carry fractional nanoseconds. Refer to IEEE 1588v2 for the representational definitions.

This input must be in the same clock domain as the lane 0 RX SerDes.
RX_PTP_TSTAMP_OUT[79:0] O RX_CLK

Time stamp for the received packet SOP corresponding to the time at which it passed the capture plane. This signal will be valid starting at the same clock cycle during which the SOP is asserted for one of the LBUS segments.

The representation of the bits contained in this bus is the same as the timer input.
RX_PTP_PCSLANE_OUT[5-1:0] O RX_CLK

This bus identifies which of the 20 PCS lanes that the SOP was detected on for the corresponding timestamp.

This signal will be valid starting at the same clock cycle during which the SOP is asserted for one of the LBUS segments.
RX_LANE_ALIGNER_FILL_0[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane0. This information can be used by the PTP application, together with the signal RX_PTP_PCSLANE_OUT[4:0], to adjust for the lane skew of the arriving SOP. The units are SerDes clock cycles.
RX_LANE_ALIGNER_FILL_1[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane1.
RX_LANE_ALIGNER_FILL_2[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane2.
RX_LANE_ALIGNER_FILL_3[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane3.
RX_LANE_ALIGNER_FILL_4[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane4.
RX_LANE_ALIGNER_FILL_5[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane5.
RX_LANE_ALIGNER_FILL_6[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane6.
RX_LANE_ALIGNER_FILL_7[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane7.
RX_LANE_ALIGNER_FILL_8[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane8.
RX_LANE_ALIGNER_FILL_9[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane9.
RX_LANE_ALIGNER_FILL_10[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane10.
RX_LANE_ALIGNER_FILL_11[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane11.
RX_LANE_ALIGNER_FILL_12[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane12.
RX_LANE_ALIGNER_FILL_13[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane13.
RX_LANE_ALIGNER_FILL_14[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane14.
RX_LANE_ALIGNER_FILL_15[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane15.
RX_LANE_ALIGNER_FILL_16[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane16.
RX_LANE_ALIGNER_FILL_17[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane17.
RX_LANE_ALIGNER_FILL_18[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane18.
RX_LANE_ALIGNER_FILL_19[7-1:0] O RX_CLK This output indicates the fill level of the alignment buffer for PCS lane19.
Table 15. DRP Path/Control Signals
Name I/O Domain Description
DRP_DO[15:0] O DRP_CLK Data bus for reading configuration data from the 100G Ethernet subsystem to the FPGA logic resources.
DRP_RDY O DRP_CLK Indicates operation is complete for write operations and data is valid for read operations.
DRP_ADDR[9:0] I DRP_CLK DRP address bus.
DRP_CLK I   DRP interface clock. When DRP is not used, this can be tied to GND.
DRP_DI[15:0] I DRP_CLK Data bus for writing configuration data from the FPGA logic resources to the 100G Ethernet subsystem.
DRP_EN I DRP_CLK

DRP enable signal.

0: No read or write operations performed.

1: Enables a read or write operation.

For write operations, DRP_WE and DRP_EN should be driven High for one DRP_CLK cycle only.
DRP_WE I DRP_CLK

DRP write enable.

0: Read operation when DRP_EN is 1.

1: Write operation when DRP_EN is 1.

For write operations, DRP_WE and DRP_EN should be driven High for one DRP_CLK cycle only.