Invalid Cycles - 3.1 English - PG203

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)
Document ID
PG203
Release Date
2025-12-17
Version
3.1 English

The following table shows several invalid TX segmented LBUS cycles as indicated by the shading.

Table 1. Invalid Segmented LBUS Cycles
Clock Cycle 1 2 3 4 5 6 7 8 9 10 -- 14 15
seg0 SOP Idle Sop Dat Dat SOP Idle Dat SOP SOP -- Dat Dat
seg1 Dat Idle Dat Dat Dat Dat Idle Dat Dat Dat Dat Dat
seg2 Dat Idle EOP Dat Dat Dat Idle Dat Idle Dat Dat Dat
seg3 EOP Idle SOP Dat Dat Dat Idle EOP EOP Dat Dat Dat
tx_rdyout 1 1 1 1 1 1 1 1 1 0 0 0
tx_ovfout 0 0 0 0 0 0 0 0 0 0 0 1

Cycle 3 is not valid because it contains two SOPs.

Cycle 5 does not contain an EOP even though there is an SOP in the next cycle.

Cycle 6 has an SOP even though the preceding packet was not closed with an EOP. This sequence is not permitted by the LBUS rules and results in undefined behavior.

Cycle 7 is idle even though tx_rdyout is asserted, and a packet transfer is already under way. This can result in buffer under-run. If this occurs, the Ethernet packet is not sent in its entirety without interruption, and a malfunction of the FCS calculation occurs.

Cycle 9 contains an idle segment during a packet transfer which is not permitted by the segmented LBUS rules.

Cycle 14 is not recommended because a data transfer is being performed even though tx_rdyout has been deasserted for the fifth consecutive cycle.

Cycle 15 must never be performed because tx_ovfout has been asserted. In the event of tx_ovfout being asserted, the 100G Ethernet subsystem should be reset.