Example Design Hierarchy (GT Subcore in Core) - 3.1 English - PG203

The following figure shows the example design hierarchy (GT subcore in core).

The preceding figure shows the instantiation of various modules and their hierarchy in the example design for the GT subcore in core configuration. The cmac_usplus_0 module instantiates the Integrated 100G Ethernet IP core and GT along with various helper blocks. Sync registers and pipeline registers are used for the synchronization of data between the core and the GT. Clocking helper blocks are used to generate the required clock frequency for the core. The cmac_usplus_0_pkt_gen_mon module instantiates cmac_usplus_0_pkt_gen (packet generator) and cmac_usplus_0_pkt_mon (packet monitor). The cmac_usplus_0_pkt_gen_mon and cmac_usplus_0 handshakes with each other using a few signals, such as GT locked, RX alignment, and data transfer signals as per LBUS protocol (more on this will be described in later sections). The cmac_usplus_0_pkt_gen module is mainly responsible for the generation of packets. It contain state machine that monitors the status of GT and the core (that is, GT lock and RX alignment) and sends traffic to the core. Similarly, the cmac_usplus_0_pkt_mon module is mainly responsible for reception and checking of packets from the core. It also contains a state machine that monitors the status of GT and the core (that is, GT lock and RX alignment) and receives traffic from the core.

Other optional modules instantiated in the example design are as follows:

• cmac_usplus_0_trans_debug: This module brings out all the DRP ports of the transceiver module out of the core. This module is present in the example design for the following conditions:
• When you select the Runtime Switchable mode in the AMD Vivado™ Integrated Design Environment (IDE), this module is used to perform the GT DRP writes to change the GT configuration (that is, from CAUI-4 to CAUI-10 / CAUI-10 to CAUI-4). After completion of the DRP write, this module generates the gt_drp_done signal that is used to reset the GT.
• When you select Enable Additional GT Control/Status and DRP Ports in the CMAC/GT Selections and Configuration Tab of the 100G Ethernet IP Vivado IDE.
• cmac_usplus_0_shared_logic_wrapper: When you select Include Shared Logic in example design in the CMAC/GT Selections and Configuration Tab of the 100G Ethernet IP Vivado IDE, this module will be available in the example design. This wrapper contains three modules cmac_usplus_0_clocking_wrapper, cmac_usplus_0_reset_wrapper and cmac_usplus_0_common wrapper. The cmac_usplus_0_clocking_wrapper has the instantiation of the IBUFDS for the gt_ref_clk and the cmac_usplus_0_reset_wrapper brings out the reset architecture instantiated in between the core and the GT. The cmac_usplus_0_common_wrapper brings the transceiver common module out of the 100G Ethernet IP core.
• Pipeline registers: Single-stage pipeline registers are introduced between the core and the transceiver when you select Enable Pipeline register in the CMAC/GT Selections and Configuration Tab. This includes a one-stage pipeline register between the core macro and the transceiver to ease timing, using the gt_txusrclk2 and gt_rxusrclk2 for the TX and RX paths respectively.
• TX/RX Sync register: The TX Sync register double synchronizes the data between the core and the transceiver with respect to the tx_clk . The RX Sync register double synchronizes the data between the transceiver and the core with respect to the rx_serdes_clk.
• rx_ptp_adjust_top: When you select Enable time stamping in the General Tab, this module is present inside the packet monitor module. This soft logic improves timestamp accuracy and compensate for the lane alignment FIFO fill levels by adding or subtracting the relative fill level of the selected lane. This module has a window averaging block with fixed window size of 32.
• cmac_usplus_0_axi4_lite_if_wrapper: When you select Include AXI4-Lite Control and Statistics Interface in the General Tab, this module will be included inside cmac_usplus_0_wrapper. This wrapper contains two modules cmac_usplus_0_axi4_lite_reg_map and cmac_usplus_0_axi4_lite_slave_2_ipif. The details of these modules are described in AXI4-Lite Interface Implementation.
• cmac_usplus_0_axi4_lite_user_if: When you select Include AXI4-Lite Control and Statistics Interface in the General Tab, this module will be present inside the cmac_usplus_0_pkt_gen_mon. The details of this module is described AXI4-Lite Interface Implementation.