The dynamic reconfiguration port (DRP)
allows the dynamic change of attributes to the 100G Ethernet subsystem. The DRP interface is a
processor-friendly synchronous interface with an address bus (DRP_ADDR) and separated data buses for reading (DRP_DO)
and writing (DRP_DI) configuration data to the CMAC block. An
enable signal (DRP_EN), a read/write signal (DRP_WE), and a ready/valid signal (DRP_RDY) are the control signals that implement read and write operations, indicate
that the operation is completion, or indicate the availability of data.
For the DRP to work, a clock must be provided to the
DRP_CLK port. See the Virtex UltraScale Architecture Data Sheet:
Virtex
UltraScale FPGAs Data Sheet: DC and AC Switching
Characteristics (DS893), for the maximum allowed clock frequency.
The CMAC block must be held in reset when
you want to dynamically change the attributes through the DRP. That is, TX_RESET, RX_RESET, and the RX_SERDES_RESET[9:0] need to be asserted High.