DRP Address Map of the CMAC Block - 3.1 English - PG203

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)
Document ID
PG203
Release Date
2025-12-17
Version
3.1 English

The following table lists the DRP map of the CMAC block sorted by address.

Table 1. DRP Map of the CMAC Block
DRP Address (Hex) DRP Bits R/W Attribute Name Attribute Encoding (Hex) DRP Encoding (Hex)
0 0 R/W CTL_TX_PTP_1STEP_ENABLE FALSE 0
TRUE 1
1 0 R/W CTL_TX_IGNORE_FCS FALSE 0
TRUE 1
2 0 R/W CTL_TX_FCS_INS_ENABLE FALSE 0
TRUE 1
6 [15:0] R/W CTL_TX_OPCODE_GPP[15:0] 0-FFFF 0-FFFF
7 [15:0] R/W CTL_TX_ETHERTYPE_PPP[15:0]] 0-FFFF 0-FFFF
8 [15:0] R/W CTL_TX_OPCODE_PPP[15:0] 0-FFFF 0-FFFF
C [15:0] R/W CTL_TX_VL_LENGTH_MINUS1[15:0] 0-FFFF 0-FFFF
D [3:0] R/W CTL_TX_IPG_VALUE[3:0] 0-F 0-F
12 [15:0] R/W CTL_TX_SA_GPP[15:0] 0-FFFF 0-FFFF
13 [15:0] R/W CTL_TX_SA_GPP[31:16] 0-FFFF 0-FFFF
14 [15:0] R/W CTL_TX_SA_GPP[47:32] 0-FFFF 0-FFFF
18 [15:0] R/W CTL_TX_DA_PPP[15:0] 0-FFFF 0-FFFF
15 [15:0] R/W CTL_TX_DA_PPP[31:16] 0-FFFF 0-FFFF
16 [15:0] R/W CTL_TX_DA_PPP[47:32] 0-FFFF 0-FFFF
1E [15:0] R/W CTL_TX_SA_PPP[15:0] 0-FFFF 0-FFFF
1F [15:0] R/W CTL_TX_SA_PPP[31:16] 0-FFFF 0-FFFF
20 [15:0] R/W CTL_TX_SA_PPP[47:32] 0-FFFF 0-FFFF
24 [15:0] R/W CTL_TX_DA_GPP[15:0] 0-FFFF 0-FFFF
25 [15:0] R/W CTL_TX_DA_GPP[31:16] 0-FFFF 0-FFFF
26 [15:0] R/W CTL_TX_DA_GPP[47:32] 0-FFFF 0-FFFF
2A [15:0] R/W CTL_TX_VL_MARKER_ID0[15:0] 0-FFFF 0-FFFF
2B [15:0] R/W CTL_TX_VL_MARKER_ID0[31:16] 0-FFFF 0-FFFF
2C [15:0] R/W CTL_TX_VL_MARKER_ID0[47:32] 0-FFFF 0-FFFF
2D [15:0] R/W CTL_TX_VL_MARKER_ID0[63:48] 0-FFFF 0-FFFF
30 [15:0] R/W CTL_TX_VL_MARKER_ID1[15:0] 0-FFFF 0-FFFF
31 [15:0] R/W CTL_TX_VL_MARKER_ID1[31:16] 0-FFFF 0-FFFF
32 [15:0] R/W CTL_TX_VL_MARKER_ID1[47:32] 0-FFFF 0-FFFF
33 [15:0] R/W CTL_TX_VL_MARKER_ID1[63:48] 0-FFFF 0-FFFF
36 [15:0] R/W CTL_TX_VL_MARKER_ID2[15:0] 0-FFFF 0-FFFF
37 [15:0] R/W CTL_TX_VL_MARKER_ID2[31:16] 0-FFFF 0-FFFF
38 [15:0] R/W CTL_TX_VL_MARKER_ID2[47:32] 0-FFFF 0-FFFF
39 [15:0] R/W CTL_TX_VL_MARKER_ID2[63:48] 0-FFFF 0-FFFF
3C [15:0] R/W CTL_TX_VL_MARKER_ID3[15:0] 0-FFFF 0-FFFF
3D [15:0] R/W CTL_TX_VL_MARKER_ID3[31:16] 0-FFFF 0-FFFF
3E [15:0] R/W CTL_TX_VL_MARKER_ID3[47:32] 0-FFFF 0-FFFF
3F [15:0] R/W CTL_TX_VL_MARKER_ID3[63:48] 0-FFFF 0-FFFF
42 [15:0] R/W CTL_TX_VL_MARKER_ID4[15:0] 0-FFFF 0-FFFF
43 [15:0] R/W CTL_TX_VL_MARKER_ID4[31:16] 0-FFFF 0-FFFF
44 [15:0] R/W CTL_TX_VL_MARKER_ID4[47:32] 0-FFFF 0-FFFF
45 [15:0] R/W CTL_TX_VL_MARKER_ID4[63:48] 0-FFFF 0-FFFF
48 [15:0] R/W CTL_TX_VL_MARKER_ID5[15:0] 0-FFFF 0-FFFF
49 [15:0] R/W CTL_TX_VL_MARKER_ID5[31:16] 0-FFFF 0-FFFF
4A [15:0] R/W CTL_TX_VL_MARKER_ID5[47:32] 0-FFFF 0-FFFF
4B [15:0] R/W CTL_TX_VL_MARKER_ID5[63:48] 0-FFFF 0-FFFF
4E [15:0] R/W CTL_TX_VL_MARKER_ID6[15:0] 0-FFFF 0-FFFF
4F [15:0] R/W CTL_TX_VL_MARKER_ID6[31:16] 0-FFFF 0-FFFF
50 [15:0] R/W CTL_TX_VL_MARKER_ID6[47:32] 0-FFFF 0-FFFF
51 [15:0] R/W CTL_TX_VL_MARKER_ID6[63:48] 0-FFFF 0-FFFF
54 [15:0] R/W CTL_TX_VL_MARKER_ID7[15:0] 0-FFFF 0-FFFF
55 [15:0] R/W CTL_TX_VL_MARKER_ID7[31:16] 0-FFFF 0-FFFF
56 [15:0] R/W CTL_TX_VL_MARKER_ID7[47:32] 0-FFFF 0-FFFF
57 [15:0] R/W CTL_TX_VL_MARKER_ID7[63:48] 0-FFFF 0-FFFF
5A [15:0] R/W CTL_TX_VL_MARKER_ID8[15:0] 0-FFFF 0-FFFF
5B [15:0] R/W CTL_TX_VL_MARKER_ID8[31:16] 0-FFFF 0-FFFF
5C [15:0] R/W CTL_TX_VL_MARKER_ID8[47:32] 0-FFFF 0-FFFF
5D [15:0] R/W CTL_TX_VL_MARKER_ID8[63:48] 0-FFFF 0-FFFF
60 [15:0] R/W CTL_TX_VL_MARKER_ID9[15:0] 0-FFFF 0-FFFF
61 [15:0] R/W CTL_TX_VL_MARKER_ID9[31:16] 0-FFFF 0-FFFF
62 [15:0] R/W CTL_TX_VL_MARKER_ID9[47:32] 0-FFFF 0-FFFF
63 [15:0] R/W CTL_TX_VL_MARKER_ID9[63:48] 0-FFFF 0-FFFF
66 [15:0] R/W CTL_TX_VL_MARKER_ID10[15:0] 0-FFFF 0-FFFF
67 [15:0] R/W CTL_TX_VL_MARKER_ID10[31:16] 0-FFFF 0-FFFF
68 [15:0] R/W CTL_TX_VL_MARKER_ID10[47:32] 0-FFFF 0-FFFF
69 [15:0] R/W CTL_TX_VL_MARKER_ID10[63:48] 0-FFFF 0-FFFF
6C [15:0] R/W CTL_TX_VL_MARKER_ID11[15:0] 0-FFFF 0-FFFF
6D [15:0] R/W CTL_TX_VL_MARKER_ID11[31:16] 0-FFFF 0-FFFF
6E [15:0] R/W CTL_TX_VL_MARKER_ID11[47:32] 0-FFFF 0-FFFF
6F [15:0] R/W CTL_TX_VL_MARKER_ID11[63:48] 0-FFFF 0-FFFF
72 [15:0] R/W CTL_TX_VL_MARKER_ID12[15:0] 0-FFFF 0-FFFF
73 [15:0] R/W CTL_TX_VL_MARKER_ID12[31:16] 0-FFFF 0-FFFF
74 [15:0] R/W CTL_TX_VL_MARKER_ID12[47:32] 0-FFFF 0-FFFF
75 [15:0] R/W CTL_TX_VL_MARKER_ID12[63:48] 0-FFFF 0-FFFF
78 [15:0] R/W CTL_TX_VL_MARKER_ID13[15:0] 0-FFFF 0-FFFF
79 [15:0] R/W CTL_TX_VL_MARKER_ID13[31:16] 0-FFFF 0-FFFF
7A [15:0] R/W CTL_TX_VL_MARKER_ID13[47:32] 0-FFFF 0-FFFF
7B [15:0] R/W CTL_TX_VL_MARKER_ID13[63:48] 0-FFFF 0-FFFF
7E [15:0] R/W CTL_TX_VL_MARKER_ID14[15:0] 0-FFFF 0-FFFF
7F [15:0] R/W CTL_TX_VL_MARKER_ID14[31:16] 0-FFFF 0-FFFF
80 [15:0] R/W CTL_TX_VL_MARKER_ID14[47:32] 0-FFFF 0-FFFF
81 [15:0] R/W CTL_TX_VL_MARKER_ID14[63:48] 0-FFFF 0-FFFF
84 [15:0] R/W CTL_TX_VL_MARKER_ID15[15:0] 0-FFFF 0-FFFF
85 [15:0] R/W CTL_TX_VL_MARKER_ID15[31:16] 0-FFFF 0-FFFF
86 [15:0] R/W CTL_TX_VL_MARKER_ID15[47:32] 0-FFFF 0-FFFF
87 [15:0] R/W CTL_TX_VL_MARKER_ID15[63:48] 0-FFFF 0-FFFF
8A [15:0] R/W CTL_TX_VL_MARKER_ID16[15:0] 0-FFFF 0-FFFF
8B [15:0] R/W CTL_TX_VL_MARKER_ID16[31:16] 0-FFFF 0-FFFF
8C [15:0] R/W CTL_TX_VL_MARKER_ID16[47:32] 0-FFFF 0-FFFF
8D [15:0] R/W CTL_TX_VL_MARKER_ID16[63:48] 0-FFFF 0-FFFF
90 [15:0] R/W CTL_TX_VL_MARKER_ID17[15:0] 0-FFFF 0-FFFF
91 [15:0] R/W CTL_TX_VL_MARKER_ID17[31:16] 0-FFFF 0-FFFF
92 [15:0] R/W CTL_TX_VL_MARKER_ID17[47:32] 0-FFFF 0-FFFF
93 [15:0] R/W CTL_TX_VL_MARKER_ID17[63:48] 0-FFFF 0-FFFF
96 [15:0] R/W CTL_TX_VL_MARKER_ID18[15:0] 0-FFFF 0-FFFF
97 [15:0] R/W CTL_TX_VL_MARKER_ID18[31:16] 0-FFFF 0-FFFF
98 [15:0] R/W CTL_TX_VL_MARKER_ID18[47:32] 0-FFFF 0-FFFF
99 [15:0] R/W CTL_TX_VL_MARKER_ID18[63:48] 0-FFFF 0-FFFF
9C [15:0] R/W CTL_TX_VL_MARKER_ID19[15:0] 0-FFFF 0-FFFF
9D [15:0] R/W CTL_TX_VL_MARKER_ID19[31:16] 0-FFFF 0-FFFF
9E [15:0] R/W CTL_TX_VL_MARKER_ID19[47:32] 0-FFFF 0-FFFF
9F [15:0] R/W CTL_TX_VL_MARKER_ID19[63:48] 0-FFFF 0-FFFF
A2 0 R/W CTL_RX_CHECK_PREAMBLE FALSE 0
TRUE 1
A3 0 R/W CTL_RX_IGNORE_FCS FALSE 0
TRUE 1
A4 0 R/W CTL_RX_FORWARD_CONTROL FALSE 0
TRUE 1
A5 0 R/W CTL_RX_DELETE_FCS FALSE 0
TRUE 1
A8 0 R/W CTL_RX_CHECK_ACK FALSE 0
TRUE 1
A9 0 R/W CTL_RX_CHECK_SFD FALSE 0
TRUE 1
AA 0 R/W CTL_RX_PROCESS_LFI FALSE 0
TRUE 1
AE [7:0] R/W CTL_RX_MIN_PACKET_LEN[7:0] 40-FF 40-FF
AF [14:0] R/W CTL_RX_MAX_PACKET_LEN[14:0] 40-3FFF 40-3FFF
B0 [15:0] R/W CTL_TX_ETHERTYPE_GPP[15:0] 0-FFFF 0-FFFF
B1 [15:0] R/W CTL_RX_OPCODE_GPP[15:0] 0-FFFF 0-FFFF
B4 [15:0] R/W CTL_RX_OPCODE_MAX_GCP[15:0] 0-FFFF 0-FFFF
B5 [15:0] R/W CTL_RX_ETYPE_PPP[15:0] 0-FFFF 0-FFFF
B6 [15:0] R/W CTL_RX_ETYPE_GCP[15:0] 0-FFFF 0-FFFF
B7 [15:0] R/W CTL_RX_VL_LENGTH_MINUS1[15:0] 0-FFFF 0-FFFF
BA [15:0] R/W CTL_RX_OPCODE_MAX_PCP[15:0] 0-FFFF 0-FFFF
BB [15:0] R/W CTL_RX_OPCODE_MIN_GCP[15:0] 0-FFFF 0-FFFF
BC [15:0] R/W CTL_RX_ETYPE_GPP[15:0] 0-FFFF 0-FFFF
BD [15:0] R/W CTL_RX_OPCODE_MIN_PCP[15:0] 0-FFFF 0-FFFF
C0 [15:0] R/W CTL_RX_ETYPE_PCP[15:0] 0-FFFF 0-FFFF
C1 [15:0] R/W CTL_RX_OPCODE_PPP[15:0] 0-FFFF 0-FFFF
C6 [15:0] R/W CTL_RX_PAUSE_DA_MCAST[15:0] 0-FFFF 0-FFFF
C7 [15:0] R/W CTL_RX_PAUSE_DA_MCAST[31:16] 0-FFFF 0-FFFF
C8 [15:0] R/W CTL_RX_PAUSE_DA_MCAST[47:32] 0-FFFF 0-FFFF
CC [15:0] R/W CTL_RX_PAUSE_DA_UCAST[15:0] 0-FFFF 0-FFFF
CD [15:0] R/W CTL_RX_PAUSE_DA_UCAST[31:16] 0-FFFF 0-FFFF
CE [15:0] R/W CTL_RX_PAUSE_DA_UCAST[47:32] 0-FFFF 0-FFFF
D2 [15:0] R/W CTL_RX_PAUSE_SA[15:0] 0-FFFF 0-FFFF
D3 [15:0] R/W CTL_RX_PAUSE_SA[31:16] 0-FFFF 0-FFFF
D4 [15:0] R/W CTL_RX_PAUSE_SA[47:32] 0-FFFF 0-FFFF
D8 [15:0] R/W CTL_RX_VL_MARKER_ID0[15:0] 0-FFFF 0-FFFF
D9 [15:0] R/W CTL_RX_VL_MARKER_ID0[31:16] 0-FFFF 0-FFFF
DA [15:0] R/W CTL_RX_VL_MARKER_ID0[47:32] 0-FFFF 0-FFFF
DB [15:0] R/W CTL_RX_VL_MARKER_ID0[63:48] 0-FFFF 0-FFFF
DE [15:0] R/W CTL_RX_VL_MARKER_ID1[15:0] 0-FFFF 0-FFFF
DF [15:0] R/W CTL_RX_VL_MARKER_ID1[31:16] 0-FFFF 0-FFFF
E0 [15:0] R/W CTL_RX_VL_MARKER_ID1[47:32] 0-FFFF 0-FFFF
E1 [15:0] R/W CTL_RX_VL_MARKER_ID1[63:48] 0-FFFF 0-FFFF
E4 [15:0] R/W CTL_RX_VL_MARKER_ID2[15:0] 0-FFFF 0-FFFF
E5 [15:0] R/W CTL_RX_VL_MARKER_ID2[31:16] 0-FFFF 0-FFFF
E6 [15:0] R/W CTL_RX_VL_MARKER_ID2[47:32] 0-FFFF 0-FFFF
E7 [15:0] R/W CTL_RX_VL_MARKER_ID2[63:48] 0-FFFF 0-FFFF
EA [15:0] R/W CTL_RX_VL_MARKER_ID3[15:0] 0-FFFF 0-FFFF
EB [15:0] R/W CTL_RX_VL_MARKER_ID3[31:16] 0-FFFF 0-FFFF
EC [15:0] R/W CTL_RX_VL_MARKER_ID3[47:32] 0-FFFF 0-FFFF
ED [15:0] R/W CTL_RX_VL_MARKER_ID3[63:48] 0-FFFF 0-FFFF
F0 [15:0] R/W CTL_RX_VL_MARKER_ID4[15:0] 0-FFFF 0-FFFF
F1 [15:0] R/W CTL_RX_VL_MARKER_ID4[31:16] 0-FFFF 0-FFFF
F2 [15:0] R/W CTL_RX_VL_MARKER_ID4[47:32] 0-FFFF 0-FFFF
F3 [15:0] R/W CTL_RX_VL_MARKER_ID4[63:48] 0-FFFF 0-FFFF
F6 [15:0] R/W CTL_RX_VL_MARKER_ID5[15:0] 0-FFFF 0-FFFF
F7 [15:0] R/W CTL_RX_VL_MARKER_ID5[31:16] 0-FFFF 0-FFFF
F8 [15:0] R/W CTL_RX_VL_MARKER_ID5[47:32] 0-FFFF 0-FFFF
F9 [15:0] R/W CTL_RX_VL_MARKER_ID5[63:48] 0-FFFF 0-FFFF
FC [15:0] R/W CTL_RX_VL_MARKER_ID6[15:0] 0-FFFF 0-FFFF
FD [15:0] R/W CTL_RX_VL_MARKER_ID6[31:16] 0-FFFF 0-FFFF
FE [15:0] R/W CTL_RX_VL_MARKER_ID6[47:32] 0-FFFF 0-FFFF
FF [15:0] R/W CTL_RX_VL_MARKER_ID6[63:48] 0-FFFF 0-FFFF
102 [15:0] R/W CTL_RX_VL_MARKER_ID7[15:0] 0-FFFF 0-FFFF
103 [15:0] R/W CTL_RX_VL_MARKER_ID7[31:16] 0-FFFF 0-FFFF
104 [15:0] R/W CTL_RX_VL_MARKER_ID7[47:32] 0-FFFF 0-FFFF
105 [15:0] R/W CTL_RX_VL_MARKER_ID7[63:48] 0-FFFF 0-FFFF
108 [15:0] R/W CTL_RX_VL_MARKER_ID8[15:0] 0-FFFF 0-FFFF
109 [15:0] R/W CTL_RX_VL_MARKER_ID8[31:16] 0-FFFF 0-FFFF
10A [15:0] R/W CTL_RX_VL_MARKER_ID8[47:32] 0-FFFF 0-FFFF
10B [15:0] R/W CTL_RX_VL_MARKER_ID8[63:48] 0-FFFF 0-FFFF
10E [15:0] R/W CTL_RX_VL_MARKER_ID9[15:0] 0-FFFF 0-FFFF
10F [15:0] R/W CTL_RX_VL_MARKER_ID9[31:16] 0-FFFF 0-FFFF
110 [15:0] R/W CTL_RX_VL_MARKER_ID9[47:32] 0-FFFF 0-FFFF
111 [15:0] R/W CTL_RX_VL_MARKER_ID9[63:48] 0-FFFF 0-FFFF
114 [15:0] R/W CTL_RX_VL_MARKER_ID10[15:0] 0-FFFF 0-FFFF
115 [15:0] R/W CTL_RX_VL_MARKER_ID10[31:16] 0-FFFF 0-FFFF
116 [15:0] R/W CTL_RX_VL_MARKER_ID10[47:32] 0-FFFF 0-FFFF
117 [15:0] R/W CTL_RX_VL_MARKER_ID10[63:48] 0-FFFF 0-FFFF
11A [15:0] R/W CTL_RX_VL_MARKER_ID11[15:0] 0-FFFF 0-FFFF
11B [15:0] R/W CTL_RX_VL_MARKER_ID11[31:16] 0-FFFF 0-FFFF
11C [15:0] R/W CTL_RX_VL_MARKER_ID11[47:32] 0-FFFF 0-FFFF
11D [15:0] R/W CTL_RX_VL_MARKER_ID11[63:48] 0-FFFF 0-FFFF
120 [15:0] R/W CTL_RX_VL_MARKER_ID12[15:0] 0-FFFF 0-FFFF
121 [15:0] R/W CTL_RX_VL_MARKER_ID12[31:16] 0-FFFF 0-FFFF
122 [15:0] R/W CTL_RX_VL_MARKER_ID12[47:32] 0-FFFF 0-FFFF
123 [15:0] R/W CTL_RX_VL_MARKER_ID12[63:48] 0-FFFF 0-FFFF
126 [15:0] R/W CTL_RX_VL_MARKER_ID13[15:0] 0-FFFF 0-FFFF
127 [15:0] R/W CTL_RX_VL_MARKER_ID13[31:16] 0-FFFF 0-FFFF
128 [15:0] R/W CTL_RX_VL_MARKER_ID13[47:32] 0-FFFF 0-FFFF
129 [15:0] R/W CTL_RX_VL_MARKER_ID13[63:48] 0-FFFF 0-FFFF
12C [15:0] R/W CTL_RX_VL_MARKER_ID14[15:0] 0-FFFF 0-FFFF
12D [15:0] R/W CTL_RX_VL_MARKER_ID14[31:16] 0-FFFF 0-FFFF
12E [15:0] R/W CTL_RX_VL_MARKER_ID14[47:32] 0-FFFF 0-FFFF
12F [15:0] R/W CTL_RX_VL_MARKER_ID14[63:48] 0-FFFF 0-FFFF
132 [15:0] R/W CTL_RX_VL_MARKER_ID15[15:0] 0-FFFF 0-FFFF
133 [15:0] R/W CTL_RX_VL_MARKER_ID15[31:16] 0-FFFF 0-FFFF
134 [15:0] R/W CTL_RX_VL_MARKER_ID15[47:32] 0-FFFF 0-FFFF
135 [15:0] R/W CTL_RX_VL_MARKER_ID15[63:48] 0-FFFF 0-FFFF
138 [15:0] R/W CTL_RX_VL_MARKER_ID16[15:0] 0-FFFF 0-FFFF
139 [15:0] R/W CTL_RX_VL_MARKER_ID16[31:16] 0-FFFF 0-FFFF
13A [15:0] R/W CTL_RX_VL_MARKER_ID16[47:32] 0-FFFF 0-FFFF
13B [15:0] R/W CTL_RX_VL_MARKER_ID16[63:48] 0-FFFF 0-FFFF
13E [15:0] R/W CTL_RX_VL_MARKER_ID17[15:0] 0-FFFF 0-FFFF
13F [15:0] R/W CTL_RX_VL_MARKER_ID17[31:16] 0-FFFF 0-FFFF
140 [15:0] R/W CTL_RX_VL_MARKER_ID17[47:32] 0-FFFF 0-FFFF
141 [15:0] R/W CTL_RX_VL_MARKER_ID17[63:48] 0-FFFF 0-FFFF
144 [15:0] R/W CTL_RX_VL_MARKER_ID18[15:0] 0-FFFF 0-FFFF
145 [15:0] R/W CTL_RX_VL_MARKER_ID18[31:16] 0-FFFF 0-FFFF
146 [15:0] R/W CTL_RX_VL_MARKER_ID18[47:32] 0-FFFF 0-FFFF
147 [15:0] R/W CTL_RX_VL_MARKER_ID18[63:48] 0-FFFF 0-FFFF
14A [15:0] R/W CTL_RX_VL_MARKER_ID19[15:0] 0-FFFF 0-FFFF
14B [15:0] R/W CTL_RX_VL_MARKER_ID19[31:16] 0-FFFF 0-FFFF
14C [15:0] R/W CTL_RX_VL_MARKER_ID19[47:32] 0-FFFF 0-FFFF
14D [15:0] R/W CTL_RX_VL_MARKER_ID19[63:48] 0-FFFF 0-FFFF
150 0 R/W TEST_MODE_PIN_CHAR FALSE 0
TRUE 1
151 0 R/W CTL_PTP_TRANSPCLK_MODE FALSE 0
TRUE 1
152 0 R/W CTL_TEST_MODE_PIN_CHAR FALSE 0
TRUE 1
156 [10:0] R/W CTL_TX_PTP_LATENCY_ADJUST[10:0] 0-7FF 0-7FF
157 [1:0] R/W CTL_RX_RSFEC_FILL_ADJUST[1:0] 0-3 0-3
158 [8:0] R/W CTL_RX_RSFEC_AM_THRESHOLD[8:0] 0-1FF 0-1FF
159 0 R/W CTL_TX_CUSTOM_PREAMBLE_ENABLE FALSE 0
TRUE 1