Constraining the Subsystem - 3.1 English

UltraScale+ Devices Integrated 100G Ethernet Subsystem LogiCORE IP Product Guide (PG203)

Document ID
PG203
Release Date
2024-07-17
Version
3.1 English

This section contains information about constraining the core in the AMD Vivado™ Design Suite.

Required Constraints

The AMD UltraScale+™ Devices Integrated Block for 100G Ethernet IP core solution requires the specification of timing and other physical implementation constraints to meet the specified performance requirements. These constraints are provided in a XDC file. Pinouts and hierarchy names in the generated XDC correspond to the provided example design of the 100G Ethernet IP core.

To achieve consistent implementation results, an XDC containing these original, unmodified constraints must be used when a design is run through the AMD tools. For additional details on the definition and use of an XDC or specific constraints, see the Vivado Design Suite User Guide: Using Constraints (UG903).

Constraints provided in the 100G Ethernet IP core have been verified through implementation and provide consistent results. Constraints can be modified, but modifications should only be made with a thorough understanding of the effect of each constraint.

Device, Package, and Speed Grade Selections

This section is not applicable for this IP core.

Clock Frequencies

This section is not applicable for this IP core.

Clock Management

This section is not applicable for this IP core.

Clock Placement

This section is not applicable for this IP core.

Banking

This section is not applicable for this IP core.

Transceiver Placement

This section is not applicable for this IP core.

I/O Standard and Placement

This section is not applicable for this IP core.