If you want to instantiate AXI4-Lite interface to access the control and status registers of the core, select Include AXI4-Lite Control and Statistics Interface in the General tab. It enables the cmac_usplus_0_axi4_lite_if_wrapper module (that contains cmac_usplus_0_axi4_lite_reg_map along with the cmac_usplus_0_axi4_lite_slave_2_ipif module) in cmac_usplus_0_wrapper. The user interface logic (cmac_usplus_0_axi4_lite_user_if) for accessing the registers (control, status and statistics) is present in the cmac_usplus_0_pkt_gen_mon module.
This mode enables the following features:
- You can configure all the CTL ports of the core through the AXI4-Lite interface. This operation is performed by writing to a set of address locations with the required data to the register map interface. The address location with the configuration register list is mentioned in Configuration Register Space.
- You can access all the status and statistics registers from the core through the AXI4-Lite interface. This is performed by reading the address locations for the status and statistics registers through register map. Configuration Register Space shows the address with the corresponding register descriptions.
The following diagram shows the implementation when Include AXI4-Lite Control and Statistics Interface is enabled in the General tab.
The following sections provide the AXI4-Lite interface state machine control and ports.