Resets - 4.3 English - PG202

MIPI D-PHY LogiCORE IP Product Guide (PG202)
Document ID
PG202
Release Date
2024-12-04
Version
4.3 English

The active-High reset signal core_rst is used in the MIPI D-PHY Controller.

The following figure shows the power-on reset behavior for the MIPI D-PHY Controller.

  1. The core_rst signal is asserted for forty core_clk cycles. Forty clock cycles are required to propagate the reset throughout the system.
  2. The mmcm_lock and pll_lock signals go Low due to core_rst assertion.
  3. The mmcm_lock signal is asserted within 100 μs after core_rst deassertion and generates the input clock for the PLL.
  4. The pll_lock signal is asserted within 100 μs after mmcm_lock assertion.
  5. LP-11 is driven on the lines for T_INIT or longer. This helps the MIPI D-PHY core complete the lane initialization. Lane initialization is indicated by the init_done internal status signal in the waveform.
  6. After LPX_PERIOD of LP-11 assertion, stopstate is asserted.
Figure 1. Power on Reset Sequence for the MIPI D-PHY Core

The following table summarizes all resets available to the MIPI D-PHY Controller and the components affected by them.

Table 1. Reset Coverage
Functional Block core_rst DPHY_EN (Core Enable from Register) SRST (Soft Reset from Register) s_axi_aresetn
TX/RX PCS Yes Yes Yes No
TX/RX PHY Yes Yes No No
Registers Yes Yes Yes Yes
Lane Initialization Yes Yes No No

The following figure shows the MIPI D-PHY TX IP and MIPI RX IP connected in a system. Config 1 and Config 2 can be in the same or multiple device(s)/board(s).

Figure 2. MIPI D-PHY TX and RX System

The following figure shows the reset assertion sequence for MIPI D PHY Core:

Figure 3. Reset Assertion Sequence for MIPI D-PHY Core