Example 9: Low-Power Receive at D-PHY RX (Slave) Side - 4.3 English - PG202

The following figure shows a single-byte data reception in low-power mode.

• The rxclkesc signal is generated by the MIPI D-PHY RX core from the data lane interconnect.
• The signal rxlpdtesc is asserted by the MIPI D-PHY RX core when the LPDT entry command is detected and stays High until the data lane returns to the Stop state, indicating that the LPDT transmission has finished.
• rxdataesc[7:0] is valid when rxvalidesc is asserted High.