This section describes trigger transmission operation.
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txrequestescis asserted along with the trigger value intxtriggeresc[3:0]. - Because the PPI does not have a handshake signal to report back the
trigger transmission on the serial line,
txrequestescis driven Low after 30txclkescclock cycles. The 30 clock cycles ensures that the MIPI D-PHY TX core transfers the trigger command on the serial line.
The following figure shows the trigger transmission operation.
Figure 1. Trigger Command Transmission from D-PHY TX (Master)