Example 13: RX Data Lane Initialization Using forcerxmode - 4.3 English - PG202

MIPI D-PHY LogiCORE IP Product Guide (PG202)
Document ID
PG202
Release Date
2024-12-04
Version
4.3 English

The RX data lane can be initialized using the forcerxmode signal. This behavior is shown in the following figure.

  1. forcerxmode is the asynchronous signal and is sampled using core_clk.
  2. The forcerxmode assertion resets the lane initialization status, which is shown as the init_done signal in the waveform.
  3. LP-11 should be driven on dp/dn serial lines for T_INIT or longer by the MIPI D-PHY TX (Master). This initializes the RX data lane.
  4. Stopstate is driven High after lane is initialized.
  5. forcerxmode can be deasserted by sampling stopstate.
Figure 1. RX Data Lane Initialization Using forcerxmode
Note: Back channel communication is not available from the MIPI D-PHY RX (Slave) to the MIPI D-PHY TX (Master). Hence, you are responsible for making sure that MIPI D-PHY TX drives LP-11 on serial lines after forcerxmode is asserted on the MIPI D-PHY RX core module. Otherwise, the MIPI D-PHY RX core does not complete the initialization.