CL_STATUS register (0x18 offset)
provides clock lane status and state machine control. The following table provides CL_STATUS
register bit description.
| Bits | Name | Access | Default Value | Description |
|---|---|---|---|---|
| 31:6 | Reserved | RO | 0 | Reserved |
| 5 | ERR_CONTROL | RO | 0 | Clock lane control error. This bit is applicable only for the MIPI D-PHY RX core. This bit is asserted when D-PHY RX clock lane receives erroneous High-Speed entry sequence or ULPS entry sequence or ULPS exit sequence. This bit is cleared when D-PHY RX clock lane receives stopstate on the serial lines. |
| 4 | STOP_STATE | RO | 0 | Clock lane is in the Stop state. |
| 3 | INIT_DONE | RO | 0 | Set after the lane has completed initialization. |
| 2 | ULPS | RO | 0 | Set to 1 when the core in ULPS (ULP State) mode. |
| 1:0 | MODE | RO | 0 |
|