PS-PL Configuration - 3.5 English - PG201

Zynq UltraScale+ MPSoC Processing System Product Guide
Document ID
PG201
Release Date
2023-06-16
Version
3.5 English

This page allows you to configure PS-PL interfaces including AXI, HP, and ACP bus interfaces.

Figure 4-13: PS-PL Configuration Page

X-Ref Target - Figure 4-13

PS_PL_Configuration.PNG