Upgrading - 2.1 English - PG199

When migrating from the LogiCORE DisplayPort IP to the DisplayPort TX Subsystem with the Video PHY Controller ( Video PHY Controller LogiCORE IP Product Guide (PG230)), AMD recommends removing the LogiCORE DisplayPort IP in its entirety and then implementing the DisplayPort TX Subsystem. The following notes help with the migration:

• Use the example design as a reference to ensure that all connections are correct.
• The LogiCORE DisplayPort IP integrates the transceivers whereas the transceivers reside in the Video PHY Controller of the subsystem implementation.
• The DisplayPort Subsystem has the option to have a native pixel or an AXI4-Stream interface.
• All associated signals that were part of the transceivers, reference clocks and transceiver lanes, are now part of the Video PHY Controller.
• The parameters for the number of DisplayPort lanes and the PHY data width need to match between the DisplayPort TX Subsystem and the Video PHY Controller.
• The link clock for the DisplayPort TX Subsystem is generated by the Video PHY Controller.
• The lnk_clk_[p/n] of the LogiCORE DisplayPort IP should be connected to the mgtrefclk0_pad_[p/n]_in of the Video PHY Controller.
• MMCM programming has been moved to software (if the DisplayPort TX Subsystem is configured with Buffer Bypass enabled). The recommendation is to use the example application as a reference for the MMCM programming.