Transmit – Training Issue - 2.1 English - PG199

DisplayPort 1.2 TX Subsystem LogiCORE IP Product Guide (PG199)

Document ID
PG199
Release Date
2024-12-11
Version
2.1 English

This section contains debugging steps for issues with the clock recovery or channel equalization at sink and if the Training Done is Low.

  • Try with a working sink such as the DisplayPort Analyzer sink device.
  • Use a DisplayPort v1.2a certified cable. Change the cable and check again.
  • Put a DisplayPort AUX Analyzer in the Transmit path and check if the various training stages match with the one's mentioned in Main Link Setup and Management.
  • Probe the lnk_clk output and check if the SI of the clock is within the Phase Noise mask of the respective GT.
  • Check status registers in the Video PHY Controller for Reset done (0x0020) and PLL lock Status (0x0018)