Training Pattern 2 Procedure (Symbol Recovery, Interlane Alignment) - 2.1 English - PG199

DisplayPort 1.2 TX Subsystem LogiCORE IP Product Guide (PG199)
Document ID
PG199
Release Date
2024-12-11
Version
2.1 English
  1. Turn off scrambling and set training pattern 2 in the source through direct register writes.
    • SCRAMBLING_DISABLE = 0x01
    • TRAINING_PATTERN_SET = 0x02
  2. Turn off scrambling and set training pattern 2 in the sink DPCD (0x00102 to 0x00106) through the AUX channel.
  3. Wait for aux read interval configured in TRAINING_AUX_RD_INTERVAL DPCD Register (0x0000E) then read status registers for all active lanes (0x00202 to 0x00203) through the AUX channel.
  4. Check the channel equalization, symbol lock, and interlane alignment status bits for all active lanes (0x00204) through the AUX channel.
  5. If any of these bits are not set, check for voltage swing or pre-emphasis level increase requests (0x00206 to 0x00207) and react accordingly.
  6. Run this loop up to five times. If after five iterations this has not succeeded, reduce link speed if at high speed and Return to the instructions for Training Pattern 1. If already at low speed, training fails.
  7. Signal the end of training by enabling scrambling and setting training pattern to 0x00 in the sink device (0x00102) through the AUX channel.
  8. On the source side, re-enable scrambling and turn off training.
    1. TRAINING_PATTERN_SET = 0x00
    2. SCRAMBLING_DISABLE = 0x00

At this point, training has completed.

Note: Training pattern 3 replaces training pattern 2 for 5.4 Gb/s link rate devices. See the DisplayPort Standard v1.2a for details.