Selecting the Pixel Interface - 2.1 English - PG199

DisplayPort 1.2 TX Subsystem LogiCORE IP Product Guide (PG199)

Document ID
PG199
Release Date
2024-12-11
Version
2.1 English

To determine the necessary clock for the pixel interface to support a specific resolution, it is important to know the active resolution and blanking information.

Note: In a quad pixel interface, if the resolution is not divisible by 4, you should add zeros at the end of the frame, over the video interface pixel data.

For example:

To support an active resolution of 2560 x 1600 @ 60, there are two possible blanking formats: Normal Blanking and Reduced Blanking, as defied by the VESA® standard.

2560 x 1600 @ 60 + Blanking = 3504 x 1658 @ 60

Requires a pixel clock of 348.58 MHz

2560 x 1600 @ 60 + Reduced Blanking = 2720 x 1646 @ 60

Requires a pixel clock of 268.63 MHz

Assuming a pixel clock of 150 MHz and a dual pixel interface:

2560 x 1600 @ 60 + Blanking = 3504 x 1658 @ 60 = 348.58 MHz

348.58 MHz / 2 = 172.28 MHz

2560 x 1600 @ 60 + Reduced Blanking = 2720 x 1646 @ 60 = 268.63 MHz

268.63 MHz / 2 = 134.31 MHz

With a dual pixel interface, the DisplayPort IP can support 2560 x 1600 only if there is a reduced blanking input. If full blanking support is needed, then a 4-pixel interface should be used.

The following figures show timing diagrams for the three pixel interface options.

Figure 1. Single Pixel Timing
Figure 2. Dual Pixel Timing
Figure 3. Quad Pixel Timing