Programming Sequence - 2.1 English - PG199

DisplayPort 1.2 TX Subsystem LogiCORE IP Product Guide (PG199)

Document ID
PG199
Release Date
2024-12-11
Version
2.1 English

This section contains the programming sequence for the subsystem using UHD@60 in MST mode with two streams. Program and enable the components of the DisplayPort TX Subsystem in the following order. HDCP Controller and AXI Timer address map exist when HDCP is enabled in SST mode.

  1. DisplayPort TX Core
  2. Dual Splitter
  3. Video Timing Controller