Payload Bandwidth Management - 2.1 English - PG199

DisplayPort 1.2 TX Subsystem LogiCORE IP Product Guide (PG199)

Document ID
PG199
Release Date
2024-12-11
Version
2.1 English

The following steps manage payload bandwidth in the source controller.

  1. Calculate Target_Average_StreamSymbolTimeSlotsPerMTP based on the DisplayPort Standard v1.2 or later. Program VC payload size with calculated Target_Average_StreamSymbolTimeSlotsPerMTP and align it with nearest even boundary.

    For example if the value is 13, program VC payload size for this particular stream to 14.

  2. In MST mode when GT data width is 4 bytes the VC Payload should be multiple of 4.
  3. The VC payload calculation for (1920x2200) stream, RGB color sampling, 8 Bits Per Color at 5.4 Gb/s, 4 lanes is given here.

    VC Payload Band width = LINK_RATE × Lane_count × 100 (see Table 2-61 in the VESA DisplayPort Standard v1.2a)

    = 5.4 × 4 × 100 = 2160

    Average Stream symbol Time slot per MTP = (Pixel_rate × Bits_per_pixel/8/VC Payload_Band width) × 64 (see Section 2.6.3.3 in the VESA DisplayPort Standard v1.2a)

    = (297 MHz × 24 /8/2160) × 64 = 26.4

    VC Payload Size = 2/4 symbol aligned of (Average Stream symbol Time slot per MTP)

    = 28

  4. Program VC Payload table as defined in DPCD standard.
  5. Program VC Payload table in source controller as defined in registers 12’h0x800 – 12’h0x8FC.